SM320F2812-HT Datasheet, PDF (146/155 Pages) Texas Instruments – Digital Signal Processor

SM320F2812-HT
SGUS062A – JUNE 2009 – REVISED APRIL 2010
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Table 6-56. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)⁽¹⁾
NO.
M39 t_su(DRV-CKXH)
M40 t_h(CKXH-DRV)
M41 t_su(FXL-CKXH)
M42 t_c(CKX)
(1) Not production tested.
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
Setup time, FSX low before CLKX high
Cycle time, CLKX
MASTER
SLAVE
MIN MAX
MIN MAX
P – 10
8P – 10
P – 10
8P – 10
16P + 10
2P
16P
UNIT
ns
ns
ns
ns
Table 6-57. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)^{(1) (2)}
NO.
PARAMETER
MASTER
MIN MAX
SLAVE
UNIT
MIN MAX
M34 t_h(CKXL-FXL)
Hold time, FSX low after CLKX low
P
ns
M35 t_d(FXL-CKXH)
Delay time, FSX low to CLKX high
2P
ns
M37 t_{dis(CKXL-DXHZ)}
Disable time, DX high impedance following last data bit
from CLKX low
P+6
7P + 6
ns
M38 t_d(FXL-DXV)
Delay time, FSX low to DX valid
6
4P + 6
ns
(1) Not production tested.
(2) 2P = 1/CLKG
For all SPI slave modes, CLKX has to be minimum eight CLKG cycles. Also, CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV
= 1. With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency is LSPCLK/16 , that is 4.5 MHz and P = 13.3 ns.
CLKX
FSX
DX
DR
LSB
M41
MSB
M42
M34
M35
M37
Bit 0
Bit 0
M38
M39
Bit(n-1)
Bit(n-1)
(n-2)
M40
(n-2)
(n-3)
(n-3)
(n-4)
(n-4)
Figure 6-44. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
146 Electrical Specifications
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