SM320F2812-HT Datasheet, PDF (102/155 Pages) Texas Instruments – Digital Signal Processor

SM320F2812-HT
SGUS062A – JUNE 2009 – REVISED APRIL 2010
Device
Status
Wake−up
Signal
A
B
Flushing Pipeline
X1/XCLKIN
XCLKOUT^†
C
STANDBY
D
STANDBY
www.ti.com
E
F
Normal Execution
t_w(WAKE-INT)
t_d(WAKE-STBY)
t_{d(IDLE−XCOH)}
32 SYSCLKOUT Cycles
NOTES: A. IDLE instruction is executed to put the device into STANDBY mode.
B. The PLL block responds to the STANDBY signal. SYSCLKOUT is held for approximately 32 cycles before being turned
off. This 32-cycle delay enables the CPU pipe and any other pending operations to flush properly.
C. The device is now in STANDBY mode.
D. The external wake-up signal is driven active (negative edge triggered shown as an example).
E. After a latency period, the STANDBY mode is exited.
F. Normal operation resumes. The device responds to the interrupt (if enabled).
Figure 6-14. STANDBY Entry and Exit Timing
102 Electrical Specifications
Copyright © 2009–2010, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320F2812-HT