SM320F2812-HT Datasheet, PDF (11/155 Pages) Texas Instruments – Digital Signal Processor

SM320F2812-HT
www.ti.com
Digital Signal Processor
Check for Samples: SM320F2812-HT
SGUS062A – JUNE 2009 – REVISED APRIL 2010
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• High-Performance Static CMOS Technology
• 128 Bit Security Key/Lock
– 150 MHz (6.67 ns Cycle Time)
– Protects Flash/ROM/OTP and L0/L1 SARAM
– Low Power (1.8 V Core at 135 MHz, 1.9 V,
Core at 150 MHz, 3.3 V I/O) Design
– 3.3 V Flash Voltage
• JTAG Boundary Scan Support⁽¹⁾
• High-Performance 32 Bit CPU (TMS320C28x)
– 16 × 16 and 32 x 32 MAC Operations
– 16 × 16 Dual MAC
– Harvard Bus Architecture
– Atomic Operations
– Prevents Firmware Reverse Engineering
• Three 32 Bit CPU Timers
• Motor Control Peripherals
– Two Event Managers (EVA, EVB)
– Compatible to 240xA Devices
• Serial Port Peripherals
– Serial Peripheral Interface (SPI)
– Two Serial Communications Interfaces
(SCIs), Standard UART
– Fast Interrupt Response and Processing
– Enhanced Controller Area Network (eCAN)
– Unified Memory Programming Model
– 4M Linear Program Address Reach
– 4M Linear Data Address Reach
– Code-Efficient (in C/C++ and Assembly)
– TMS320F24x/LF240x Processor Source Code
Compatible
– Multichannel Buffered Serial Port (McBSP)
With SPI Mode
• 12 Bit ADC, 16 Channels
– 2 × 8 Channel Input Multiplexer
– Two Sample-and-Hold
– Single/Simultaneous Conversions
• On-Chip Memory
– Fast Conversion Rate: 80 ns/12.5 MSPS
– Flash Devices: Up to 128K × 16 Flash (Four
8K × 16 and Six 16K × 16 Sectors)
– ROM Devices: Up to 128K × 16 ROM
– 1K × 16 OTP ROM
– L0 and L1: 2 Blocks of 4K × 16 Each
Single-Access RAM (SARAM)
• Up to 56 Individually Programmable,
Multiplexed General-Purpose Input / Output
(GPIO) Pins
• Advanced Emulation Features
– Analysis and Breakpoint Functions
– Real-Time Debug via Hardware
– H0: 1 Block of 8K × 16 SARAM
• Development Tools Include
– M0 and M1: 2 Blocks of 1K × 16 Each
SARAM
• Boot ROM (4K × 16)
– With Software Boot Modes
– Standard Math Tables
• External Interface
– ANSI C/C++ Compiler/Assembler/Linker
– Supports TMS320C24x™/240x Instructions
– Code Composer Studio™ IDE
– DSP/BIOS™
– JTAG Scan Controllers [Texas Instruments
(TI) or Third-Party]
– Up to 1M Total Memory
– Evaluation Modules
– Programmable Wait States
– Programmable Read/Write Strobe Timing
– Three Individual Chip Selects
• Clock and System Control
– Dynamic PLL Ratio Changes Supported
– Broad Third-Party Digital Motor Control
Support
• Low-Power Modes and Power Savings
– IDLE, STANDBY, HALT Modes Supported
– Disable Individual Peripheral Clocks
– On-Chip Oscillator
xxx
– Watchdog Timer Module
xxx
• Three External Interrupts
xxx
• Peripheral Interrupt Expansion (PIE) Block That
xxx
Supports 45 Peripheral Interrupts
xxx
(1) IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port
TMS320C24x, Code Composer Studio, DSP/BIOS, C28x, TMS320C2000, TMS320C54x, TMS320C55x, TMS320C28x are trademarks of
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Texas Instruments.
eZdsp is a trademark of Spectrum Digital Incorporated.
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Copyright © 2009–2010, Texas Instruments Incorporated
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