SM320F2812-HT Datasheet, PDF (122/155 Pages) Texas Instruments – Digital Signal Processor

SM320F2812-HT
SGUS062A – JUNE 2009 – REVISED APRIL 2010
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6.23 External Interface Read Timing
Table 6-34. External Memory Interface Read Switching Characteristics⁽¹⁾
PARAMETER
MIN MAX UNIT
t_{d(XCOH-XZCSL)}
t_{d(XCOHL-XZCSH)}
t_d(XCOH-XA)
t_{d(XCOHL-XRDL)}
t_d(XCOHL-XRDH
t_h(XA)XZCSH
t_h(XA)XRD
Delay time, XCLKOUT high to zone chip-select active low
Delay time, XCLKOUT high/low to zone chip-select inactive high
Delay time, XCLKOUT high to address valid
Delay time, XCLKOUT high/low to XRD active low
Delay time, XCLKOUT high/low to XRD inactive high
Hold time, address valid after zone chip-select inactive high
Hold time, address valid after XRD inactive high
1 ns
–2
3 ns
2 ns
1 ns
–2
1 ns
(2)
ns
(2)
ns
(1) Not production tested.
(2) During inactive cycles, the XINTF address bus always holds the last address put out on the bus. This includes alignment cycles.
Table 6-35. External Memory Interface Read Timing Requirements⁽¹⁾
t_a(A)
Access time, read data from address valid
t_a(XRD)
Access time, read data valid from XRD active low
t_su(XD)XRD
Setup time, read data valid before XRD strobe inactive high
t_h(XD)XRD
Hold time, read data valid after XRD inactive high
(1) Not production tested.
(2) LR = Lead period, read access. AR = Active period, read access. See Table 6-25 .
MIN
MAX UNIT
(LR + AR) – 14⁽²⁾
ns
AR – 12⁽²⁾
ns
12
ns
0
ns
Lead
Active
Trail
XCLKOUT=XTIMCLK
XCLKOUT= 1/2 XTIMCLK
XZCS0AND1, XZCS2,
XZCS6AND7
XA[0:18]
t_{d(XCOH-XZCSL)}
t_d(XCOH-XA)
t_{d(XCOHL-XZCSH)}
XRD
XWE
t_{d(XCOHL-XRDL)}
t_{d(XCOHL-XRDH)}
t_su(XD)XRD
XR/W
XD[0:15]
t_a(A)
t_a(XRD)
t_h(XD)XRD
DIN
XREADY
NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an
alignment cycle before an access to meet this requirement.
B. During alignment cycles, all signals transitions to their inactive state.
C. For USEREADY = 0, the external XREADY input signal is ignored.
D. XA[0:18] holds the last address put on the bus during inactive cycles, including alignment cycles.
Figure 6-29. Example Read Access
122 Electrical Specifications
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