SM320F2812-HT Datasheet, PDF (75/155 Pages) Texas Instruments – Digital Signal Processor

www.ti.com
Figure 4-10 shows the SCI module block diagram.
SM320F2812-HT
SGUS062A – JUNE 2009 – REVISED APRIL 2010
Frame Format and Mode
Parity
Even/Odd Enable
SCICCR.6 SCICCR.5
TXWAKE
SCICTL1.3
1
WUT
LSPCLK
SCIHBAUD. 15 − 8
Baud Rate
MSbyte
Register
SCILBAUD. 7 − 0
Baud Rate
LSbyte
Register
SCIRXST.7 SCIRXST.4 − 2
RX Error
FE OE PE
RX Error
TXSHF
Register
8
Transmitter−Data
Buffer Register
8
TX FIFO _0
TX FIFO _1
−−−−−
TX FIFO _15
SCITXBUF.7−0
TX FIFO registers
SCIFFENA
SCIFFTX.14
SCICTL1.1
TXENA
TX EMPTY
SCICTL2.6
TXRDY
SCICTL2.7
TX FIFO
Interrupts
SCITXD
TX INT ENA
SCICTL2.0
TX Interrupt
Logic
SCI TX Interrupt select logic
AutoBaud Detect logic
RXSHF
Register
RXENA
SCIRXD
RXWAKE
SCIRXST.1
8 ^SCICTL1.0
Receive Data
Buffer register
SCIRXBUF.7−0
8
RX FIFO _15
−−−−−
RX FIFO_1
RX FIFO _0
SCIRXBUF.7−0
RX FIFO registers
RXFFOVF
RXRDY
SCIRXST.6
RX FIFO
Interrupts
BRKDT
SCIRXST.5
SCICTL2.1
RX/BK INT ENA
RX Interrupt
Logic
SCIFFRX.15
TXINT
To CPU
RXINT
To CPU
RX ERR INT ENA
SCICTL1.6
SCI RX Interrupt select logic
SCITXD
SCIRXD
Figure 4-10. Serial Communications Interface (SCI) Module Block Diagram
Copyright © 2009–2010, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320F2812-HT
Peripherals
75