SM320F2812-HT Datasheet, PDF (27/155 Pages) Texas Instruments – Digital Signal Processor

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3 Functional Overview
TINT0
TINT1
XINT13
G
P
I
GPIO Pins ^O
M
U
X
XNMI
CPU-Timer 0
CPU-Timer 1
CPU-Timer 2
TINT2
PIE
(96 interrupts)^†
External Interrupt
Control
(XINT1/2/13, XNMI)
SCIA/SCIB
SPI
McBSP
FIFO
FIFO
FIFO
eCAN
EVA/EVB
SM320F2812-HT
SGUS062A – JUNE 2009 – REVISED APRIL 2010
Memory Bus
INT14
INT[12:1]
INT13
NMI
C28x CPU
Real-Time JTAG
External
Interface
(XINTF)
M0 SARAM
1K x 16
M1 SARAM
1K x 16
Control
Address(19)
Data(16)
L0 SARAM ^‡
4K x 16
L1 SARAM ^‡
4K x 16
Flash ^‡
128K x 16
16 Channels
12-Bit ADC
XRS
X1/XCLKIN
X2
XF_XPLLDIS
System Control
(Oscillator and PLL
+
Peripheral Clocking
+
Low-Power
Modes
+
WatchDog)
RS
CLKIN
Memory Bus
Peripheral Bus
† _{45 of the possible 96 interrupts are used on the device.}
‡ _{Protected by the code-security module.}
Figure 3-1. Functional Block Diagram
OTP ^‡
1K x 16
H0 SARAM
8K ⋅ 16
Boot ROM
4K ⋅ 16
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Functional Overview
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