SM320F2812-HT Datasheet, PDF (53/155 Pages) Texas Instruments – Digital Signal Processor

SM320F2812-HT
www.ti.com
SGUS062A – JUNE 2009 – REVISED APRIL 2010
In the F2812 device, the timer interrupt signals (TINT0, TINT1, TINT2) are connected as shown in
Figure 4-2.
INT1
to
INT12
PIE
TINT0
CPU-TIMER 0
C28x
INT13
INT14
TINT1
TINT2
XINT13
CPU-TIMER 1
(Reserved for TI
system functions)
CPU-TIMER 2
(Reserved for TI
system functions)
A. The timer registers are connected to the Memory Bus of the C28x processor.
B. The timing of the timers is synchronized to SYSCLKOUT of the processor clock.
Figure 4-2. CPU-Timer Interrupts Signals and Output Signal (See Notes A. and B.)
The general operation of the timer is as follows: The 32-bit counter register TIMH:TIM is loaded with the
value in the period register PRDH:PRD. The counter register, decrements at the SYSCLKOUT rate of the
C28x. When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse. The
registers listed in Table 4-1 are used to configure the timers. For more information, see the TMS320x281x
System Control and Interrupts Reference Guide (literature number SPRU078).
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