M16C26A Datasheet, PDF (98/352 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
10. Watchdog Timer
Watchdog Timer Control Register
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol
WDC
Address
000F16
After Reset
00XXXXXX 2
Bit Symbol
Bit Name
Function
RW
(b4-b0) High-order bit of watchdog timer
RO
(b6-b5) ^{Reserved bit}
Set to “0”
RW
WDC7 Prescaler select bit
0: Divided by 16
1: Divided by 128
RW
Watchdog Timer Start Register
b7
b0
Symbol
WDTS
Address
000E16
After Reset
Indeterminate
Function
RW
The watchdog timer is initialized and starts counting after a write instruction to
this register. The watchdog timer value is always initialized to “7FFF 16”
WO
regardless of whatever value is written.
Figure 10.2 WDC Register and WDTS Register
10.1 Count Source Protective Mode
In this mode, a on-chip oscillator clock is used for the watchdog timer count source. The watchdog timer
can be kept being clocked even when CPU clock stops as a result of run-away.
Before this mode can be used, the following register settings are required:
(1) Set the PRC1 bit in the PRCR register to “1” (enable writes to PM1 and PM2 registers).
(2) Set the PM12 bit in the PM1 register to “1” (reset when the watchdog timer underflows).
(3) Set the PM22 bit in the PM2 register to “1” (on-chip oscillator clock used for the watchdog timer count
source).
(4) Set the PRC1 bit in the PRCR register to “0” (disable writes to PM1 and PM2 registers).
(5) Write to the WDTS register (watchdog timer starts counting).
Setting the PM22 bit to “1” results in the following conditions
• The on-chip oscillator continues oscillating even if the CM21 bit in the CM2 register is set to "0" (main
clock or PLL clock) (system clock of count source selected by the CM21 bit is valid)
• The on-chip oscillator starts oscillating, and the in-chip oscillator clock becomes the watchdog timer count
source.
Watchdog timer count (32768)
Watchdog timer period =
on-chip oscillator clock
• The CM10 bit in the CM1 register is disabled against write. (Writing a “1” has no effect, nor is stop mode
entered.)
• The watchdog timer does not stop when in wait mode.
Rev. 2.00 Feb.15, 2007 page 81 of 329
REJ09B0202-0200