M16C26A Datasheet, PDF (161/352 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
13. Serial I/O
Table 13.1.1.3 lists the functions of the input/output pins during clock synchronous serial I/O mode. Table
13.3 shows pin functions for the case where the multiple transfer clock output pin select function is dese-
lected. Table 13.1.1.4 lists the P64 pin functions during clock synchronous serial I/O mode.
Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi
pin outputs an “H”. (If the N-channel open-drain output is selected, this pin is in a high-impedance state.)
Table 13.1.1.3. Pin Functions⁽¹⁾ (When Not Select Multiple Transfer Clock Output Pin Function)
Pin name
Function
TxDi (i = 0 to 2) _{Serial data output}
(P63, P67, P70)
Method of selection
(Outputs dummy data when performing reception only)
RxDi
Serial data input
(P62, P66, P71)
Set the PD6_2 bit and PD6_6 bit in the PD6 register, and PD7_1 bit in the PD7
register to "0"(Can be used as an input port when performing transmission only)
CLKi
Transfer clock output
(P61, P65, P72)
Transfer clock input
CTSi/RTSi
CTS input
(P60, P64, P73)
RTS output
Set the CKDIR bit in the UiMR register to "0"
Set the CKDIR bit in the UiMR register to "1"
Set the PD6_1 bit and PD6_5 bit in the PD6 register, and the PD7_2 bit in the
PD7 register to "0"
Set the CRD bit in the UiC0 register to "0"
Set the CRS bit in the UiC0 register to "0"
Set the PD6_0 bit and PD6_4 bit in the PD6 register’ is set to "0", the PD7_3
bit in the PD7 register to "0"
Set the CRD bit in the UiC0 register to "0"
Set the CRS bit in the UiC0 register to "1"
I/O port
Set the CRD bit in the UiC0 register to "1"
NOTE:
1. When the U1MAP bit in PACR register is “1” (P73 to P70), UART1 pin is assgined to P73 to P70.
Table 13.1.1.4. P64 Pin Functions⁽¹⁾
Pin function
Bit set value
U1C0 register
UCON register
PD6 register
CRD CRS RCSP CLKMD1 CLKMD0
PD6_4
P64
1
0
0
Input: 0, Output: 1
CTS1
RTS1
CTS0⁽²⁾
CLKS1
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1⁽³⁾
1
NOTES:
1. When the U1MAP bit in PACR register is “1” (P73 to P70), this table lists the P70 functions.
2. In addition to this, set the CRD bit in the U0C0 register to “0” (CT00/RT00 enabled) and theCRS bit in the
U0C0 register to “1” (RTS0 selected).
3. When the CLKMD1 bit is set to "1" and the CLKMD0 bit is set to "0", the following logiclevels are output:
• High if the CLKPOL bit in the U1C0 register is set to "0"
• Low if the CLKPOL bit in the U1C0 register is set to "1"
Rev. 2.00 Feb.15, 2007 ^{page 144} of 329
REJ09B0202-0200