M16C26A Datasheet, PDF (86/352 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
9. Interrupt
9.3.1 I Flag
The I flag enables or disables the maskable interrupt. Setting the I flag to “1” (= enabled) enables the
maskable interrupt. Setting the I flag to “0” (= disabled) disables all maskable interrupts.
9.3.2 IR Bit
The IR bit is set to “1” (= interrupt requested) when an interrupt request is generated. Then, when the
interrupt request is accepted and the CPU branches to the corresponding interrupt vector, the IR bit is
cleared to “0” (= interrupt not requested).
The IR bit can be cleared to “0” in a program. Note that do not write “1” to this bit.
9.3.3 ILVL2 to ILVL0 Bits and IPL
Interrupt priority levels can be set using the ILVL2 to ILVL0 bits.
Table 9.3.3.1 shows the settings of interrupt priority levels and Table 9.3.3.2 shows the interrupt priority
levels enabled by the IPL.
The following are conditions under which an interrupt is accepted:
· I flag is set to “1”
· IR bit is set to “1”
· interrupt priority level > IPL
The I flag, IR bit, ILVL2 to ILVL0 bits and IPL are independent of each other. In no case do they affect one
another.
Table 9.3.3.1. Settings of Interrupt Priority
Levels
ILVL2 to ILVL0 bits
Interrupt priority
level
Priority
order
0002
0012
0102
0112
1002
1012
1102
1112
Level 0 (interrupt disabled)
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
Low
High
Table 9.3.3.2. Interrupt Priority Levels
Enabled by IPL
IPL
0002
0012
0102
0112
1002
1012
1102
1112
Enabled interrupt priority levels
Interrupt levels 1 and above are enabled
Interrupt levels 2 and above are enabled
Interrupt levels 3 and above are enabled
Interrupt levels 4 and above are enabled
Interrupt levels 5 and above are enabled
Interrupt levels 6 and above are enabled
Interrupt levels 7 and above are enabled
All maskable interrupts are disabled
Rev. 2.00 Feb.15, 2007 ^{page 69} of 329
REJ09B0202-0200