M16C26A Datasheet, PDF (177/352 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
13. Serial I/O
Table 13.1.3.2. Registers to Be Used and Settings in I²C bus Mode (1) (Continued)
Register
Bit
Function
Master
Slave
U2TB 0 to 7
Set transmission data
Set transmission data
(1)
U2RB 0 to 7
Reception data can be read
Reception data can be read
(1)
8
ACK or NACK is set in this bit
ACK or NACK is set in this bit
ABT
Arbitration lost detection flag
Invalid
OER
Overrun error flag
Overrun error flag
U2BRG 0 to 7
Set a transfer rate
Invalid
U2MR SMD2 to SMD0 Set to ‘0102’
Set to ‘0102’
(1)
CKDIR
Set to “0”
Set to “1”
IOPOL
Set to “0”
Set to “0”
U2C0 CLK1, CLK0
Select the count source for the U2BRG Invalid
register
CRS
Invalid because CRD = 1
Invalid because CRD = 1
TXEPT
Transmit buffer empty flag
Transmit buffer empty flag
CRD
Set to “1”
Set to “1”
NCH
Set to “1”
Set to “1”
CKPOL
Set to “0”
Set to “0”
UFORM
Set to “1”
Set to “1”
U2C1 TE
Set this bit to “1” to enable transmission Set this bit to “1” to enable transmission
TI
Transmit buffer empty flag
Transmit buffer empty flag
RE
Set this bit to “1” to enable reception
Set this bit to “1” to enable reception
RI
Reception complete flag
Reception complete flag
U2IRS
Invalid
Invalid
U2RRM,
Set to “0”
Set to “0”
U2LCH, U2ERE
U2SMR IICM
Set to “1”
Set to “1”
ABC
Select the timing at which arbitration-lost Invalid
is detected
BBS
Bus busy flag
Bus busy flag
3 to 7
U2SMR2 IICM2
Set to “0”
Set to “0”
Refer to Table 13.1.3.4 I²C bus Mode Functions Refer to Table 13.1.3.4 I²C bus Mode Functions
CSC
Set this bit to “1” to enable clock
Set to “0”
synchronization
SWC
Set this bit to “1” to have SCL2 output Set this bit to “1” to have SCL2 output
fixed to “L” at the falling edge of the 9th fixed to “L” at the falling edge of the 9^th
bit of clock
bit of clock
ALS
Set this bit to “1” to have SDA2 output Set to “0”
stopped when arbitration-lost is detected
STAC
Set to “0”
Set this bit to “1” to initialize UART2 at
start condition detection
SWC2
Set this bit to “1” to have SCL2 output Set this bit to “1” to have SCL2 output
forcibly pulled low
forcibly pulled low
SDHI
Set this bit to “1” to disable SDA2 output Set this bit to “1” to disable SDA2 output
7
Set to “0”
Set to “0”
U2SMR3 0, 2, 4 and NODC Set to “0”
Set to “0”
CKPH
Refer to Table 13.1.3.4 I²C bus Mode Functions Refer to Table 13.1.3.4 I²C bus Mode Functions
DL2 to DL0
Set the amount of SDA2 digital delay
Set the amount of SDA2 digital delay
NOTE:
1. Not all register bits are described above. Set those bits to “0” when writing to the registers in I²C bus
mode.
Rev. 2.00 Feb.15, 2007 ^{page 160} of 329
REJ09B0202-0200