M16C26A Datasheet, PDF (102/352 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
11. DMAC
DMA1 request cause select register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DM1SL
Address
03BA16
After reset
0016
Bit symbol
Bit name
Function
RW
DSEL0 _{DMA request cause Refer to note}
RW
DSEL1 ^{select bit}
RW
DSEL2
RW
DSEL3
RW
(b5-b4)
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
DMS
DMA request cause
expansion select bit
0: Basic cause of request
1: Extended cause of request
RW
DSR
Software DMA
request bit
A DMA request is generated by
setting this bit to “1” when the DMS
bit is “0” (basic cause) and the
RW
DSEL3 to DSEL0 bits are “0001 2”
(software trigger).
The value of this bit when read is “0” .
NOTE:
1. The causes of DMA1 requests can be selected by a combination of DMS bit and DSEL3 to DSEL0 bits in the
manner described below.
DSEL3 to DSEL0
0 0 0 02
0 0 0 12
0 0 1 02
0 0 1 12
0 1 0 02
0 1 0 12
0 1 1 02
0 1 1 12
1 0 0 02
1 0 0 12
1 0 1 02
1 0 1 12
1 1 0 02
1 1 0 12
1 1 1 02
1 1 1 12
DMS=0(basic cause of request)
Falling edge of INT1 pin
Software trigger
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
Timer B0
Timer B1
Timer B2
UART0 transmit
UART0 receive
UART2 transmit
UART2 receive/ACK2
A/D conversion
UART1 receive
DMS=1(extended cause of request)
–
–
–
–
–
–
–
Two edges of INT1
–
–
–
–
–
–
–
–
DMAi control register(i=0,1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DM0CON
DM1CON
Address
002C16
003C16
After reset
00000X002
00000X002
Bit symbol
Bit name
Function
RW
DMBIT
Transfer unit bit select bit 0 : 16 bits
1 : 8 bits
RW
DMASL
Repeat transfer mode
select bit
0 : Single transfer
1 : Repeat transfer
RW
DMAS
DMA request bit
0 : DMA not requested
1 : DMA requested
RW
(1)
DMAE
DMA enable bit
0 : Disabled
1 : Enabled
RW
DSD
Source address direction _{0 : Fixed}
select bit (2)
1 : Forward
RW
DAD
Destination address
direction select bit (2)
0 : Fixed
1 : Forward
RW
(b7-b6)
Nothing is assigned. When write, set to “0”. When
read, its content is “0”.
NOTES:
1.The DMAS bit can be set to “0” by writing “0” in a program (This bit remains unchanged even if “1” is written).
2. At least one of the DAD and DSD bits must be “0” (address direction fixed).
Figure 11.3 DM1SL Register, DM0CON Register, and DM1CON Register
Rev. 2.00 Feb.15, 2007 page 85 of 329
REJ09B0202-0200