M16C26A Datasheet, PDF (93/352 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
9. Interrupt
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9.6 INT Interrupt
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INTi interrupt (i=0 to 5) is triggered by the edges of external inputs. The edge polarity is selected using the
IFSRi bit in the IFSR register.
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________
________
To use the INT4 interrupt, set the IFSR6 bit in the IFSR register to "1" (=INT4). To use the INT5 interrupt, set
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the IFSR7 bit in the IFSR register to "1" (=INT5).
After modifiying the IFSR6 or IFSR7 bit, clear the corresponding IR bit to "0" (=interrupt not requested)
before enabling the interrupt.
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The INT5 input has an effective digital debounce function for a noize rejection. Refer to 16.6 Digital
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Debounce function for this detail. When using INT5 interrupt to exit stop mode, set the P17DDR register
to "FF16" before entering stop mode.
Figure 9.6.1 shows the IFSR register.
Interrupt request cause select register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
IFSR
Address
035F16
After reset
0016
Bit symbol
Bit name
Function
RW
IFSR0
INT0 interrupt polarity
switching bit
0 : One edge
1 : Both edges (1)
RW
IFSR1
INT1 interrupt polarity
switching bit
0 : One edge
1 : Both edges (1)
RW
IFSR2 INT2 interrupt polarity
0 : One edge
switching bit
1 : Both edges (1)
RW
IFSR3 INT3 interrupt polarity
0 : One edge
switching bit
1 : Both edges (1)
RW
IFSR4 INT4 interrupt polarity
0 : One edge
switching bit
1 : Both edges ₍₁₎
RW
IFSR5 INT5 interrupt polarity
0 : One edge
switching bit
1 : Both edges (1)
RW
IFSR6 Interrupt request cause
0 : Reserved
select bit
1 : INT4
RW
IFSR7
Interrupt request cause
select bit
0 : Reserved
1 : INT5
RW
NOTE:
1. When setting this bit to “1” (= both edges), make sure the POL bit in the INT0IC to INT5IC register is set to
“0” (= falling edge).
Figure 9.6.1. IFSR Register
Rev. 2.00 Feb.15, 2007 ^{page 76} of 329
REJ09B0202-0200