M16C26A Datasheet, PDF (140/352 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
12. Timer
Timer B2 Special Mode Register ⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol
TB2SC
Address
039E16
After Reset
X00000002
Bit Symbol
Bit Name
Function
RW
PWCON Timer B2 reload timing _{0: Timer B2 underflow}
switch bit (2)
1: Timer A output at odd-numbered
RW
IVPCR1 ^{Three-phase output port} 0: Three-phase output forcible cutoff by SD pin input
SD control bit 1
(high impedance) disabled
(3, 4, 7)
1: Three-phase output forcible cutoff by SD pin input RW
(high impedance) enabled
TB0EN ^{Timer B0 operation mode} 0: Other than A/D trigger mode
select bit
1: A/D trigger mode (5)
RW
TB1EN ^{Timer B1 operation mode 0: Other than A/D trigger mode}
select bit
1: A/D trigger mode (5)
RW
TB2SEL Trigger select bit (6)
0: TB2 interrupt
1: Underflow of TB2 interrupt
RW
generation frequency setting counter [ICTB2]
(b6-b5) ^{Reserved bits}
Set to 0
RW
Nothing is assigned. If necessary, set to 0.
(b7)
When read, the content is 0.
NOTES:
1. Write to this register after setting the PRC1 bit in the PRCR register to 1 (write enabled).
2. If the INV11 bit is 0 (three-phase mode 0) or the INV06 bit is 1 (triangular wave modulation mode), set this bit to 0 (timer
B2 underflow).
3. When setting the IVPCR1 bit to 1 (three-phase output forcible cutoff by SD pin input enabled), Set the PD85 bit to 0 (= input
mode).
4. Related pins are U(P80), U(P81), V(P72), V(P73), W(P74), W(P75). When a high-level ("H") signal is applied to the SD pin
and set the IVPCR1 bit to 0 after forcible cutoff, pins U, U, V, V, W, and W are exit from the high-impedance state. If a low-
level (“L”) signal is applied to the SD pin, three-phase motor control timer output will be disabled (INV03=0). At this time,
when the IVPCR1 bit is 0, pins U, U, V, V, W, and W become programmable I/O ports. When the IVPCR1 bit is set to 1,
pins U, U, V, V, W, and W are placed in a high-impedance state regardless of which function of those pins is used.
5. When this bit is used in delayed trigger mode 0, set bits TB0EN and TB1EN to 1 (A/D trigger mode).
6. When setting the TB2SEL bit to 1 (underflow of TB2 interrupt generation frequency setting counter[ICTB2]), set the INV02
bit to 1 (three-phase motor control timer function).
The effect of SD pin input is below.
1.Case of INV03 = 1(Three-phase motor control timer output enabled)
IVPCR1 bit
SD pin inputs⁽³⁾
Status of U/V/W pins
Remarks
1
(Three-phase output
forcrible cutoff enable)
0
(Three-phase output
forcrible cutoff disable)
H
Three-phase PWM output
L⁽¹⁾
High impedance⁽⁴⁾
Three-phase output
forcrible cutoff
H
Three-phase PWM output
L⁽¹⁾
Input/output port⁽²⁾
NOTES:
1. When "L" is applied to the SD pin, INV03 bit is changed to 0 at the same time.
2. The value of the port register and the port direction register becomes effective.
3. When SD function is not used, set to 0 (Input) in PD85 and pullup to "H" in SD pin from outside.
4. To leave the high-impedance state and restart the three-phase PWM signal output after the three-phase PWM signal
output forced cutoff, set the IVPCR1 bit to 0 after the SD pin input level becomes high (“H”).
2.Case of INV03 = 0(Three-phase motor control timer output disabled)
IVPCR1 bit
SD pin inputs
Status of U/V/W pins
Remarks
1
H
(Three-phase output
forcrible cutoff enable)
L
0
H
(Three-phase output
forcrible cutoff disable)
L
Peripheral input/output
or input/output port
High impedance
Peripheral input/output
or input/output port
Peripheral input/output
or input/output port
Three-phase output
forcrible cutoff⁽¹⁾
NOTE:
1. The three-phase output forcrible cutoff function becomes effective if the INPCR1 bit is set to 1 (three-phase output
forcrible cutoff function enable) even when the INV03 bit is 0 (three-phase motor control timer output disalbe)
Figure 12.3.6. TB2SC Registers
Rev. 2.00 Feb.15, 2007 ^{page 123} of 329
REJ09B0202-0200