M16C26A Datasheet, PDF (258/352 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
17. Flash Memory Version
Flash memory control register 0
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol
FMR0
Address
01B716
After reset
000000012
Bit symbol
Bit name
FMR00 RY/BY status flag
FMR01
CPU rewrite mode select bit
(1)
FMR02
Block 0, 1 rewrite enable bit
(2)
Function
RW
0: Busy (during writing or erasing)
1: Ready
RO
0: Disables CPU rewrite mode
(Disables software command)
RW
1: Enables CPU rewrite mode
(Enables software commands)
Set write protection for user ROM area
(see Table 17.5.2.1)
RW
FMSTP ^{Flash memory stop bit}
(3, 5)
0: Starts flash memory operation
1: Stops flash memory operation
(Enters low-power consumption state _RW
and flash memory reset)
(b5-b4) ^{Reserved bit}
Set to “0”
RW
FMR06
Program status flag
(4)
0: Terminated normally
1: Terminated in error
RO
FMR07 Erase status flag
(4)
0: Terminated normally
1: Terminated in error
RO
NOTES:
1. When setting this bit to “1”, set to “1” immdediately after setting it first to “0”. Do not generate an interrupt
or a DMA transfer between setting the bit to “0” and setting it to “1”. Set this bit while the P85/NMI/SD pin
is “H” when selecting the NMI function. Set by program in a space other than the flash memory in EW0
mode. Set this bit to read alley mode and “0”
2. Set this bit to “1” immediately after setting it first to “0” while the FMR01 bit is set to “1”. Do not generate
an interrupt or a DMA transfer between setting this bit to “0” and setting it to “1”.
3. Set this bit in a pace other than the flash memory by program. When this bit is set to 1, access to flash
memory will be denied. To set this bit to 0 after setting it to 1, wait for 10 µsec. or more after setting it to
1. To read data from flash memory after setting this bit to 0, maintain tps wait time before accessing
flash memory.
4. This bit is set to “0” by executing the clear status command.
5. This bit is enabled when the FMR01 bit is set to “1” (CPU rewrite mode). This bit can be set to “1” when
the FMR01 bit is set to “0”. However, the flash memory does not enter low-power consumption status
Flash memory control register 1
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
FMR1
Address
01B516
After reset
000XXX0X 2
Bit symbol
Bit name
Function
RW
(b0) Reserved bit
When read, its content is indeterminate RO
FMR11 EW1 mode select bit (1)
0: EW0 mode
1: EW1 mode
RW
(b3-b2) ^{Reserved bit}
When read, its content is indeterminate _RO
Nothing is assigned. When write, set to “0”.
(b4) _{When read, its contect is indeterminate.}
(b5) ^{Reserved bit}
Set to “0”
RW
FMR16 ^{Block 0 to 3 rewrite enable}
bit (2)
FMR17 Block A, B access wait bit
(3)
Set write protection for user ROM area
(see Table 17.5.2.1)
RW
0: Disable
1: Enable
0: PM17 enabled
RW
1: With wait state (1 wait)
NOTES:
1. Set this bit to “1” immediately after setting it first to “0”. Do not generate an interrupt or a DMA transfer
between setting the bit to “0” and setting it to “1”. Set this bit while the P85/NMI/SD pin is “H” when the
NMI function is selected. If the FMR01 bit is set to “0”, the FMR01 bit and FMR11 bit are both set to “0”
2. Set this bit to “1” immediately after setting it first to “0”. Do not generate an interrupt or a DMA transfer
after setting to “0”.
3. When rewriting more than 100 times, set this bit to “1” (with wait state). When the FMR17 bit is “1” (with
wait state), regardless of the content of the PM17 bit, 1 wait is inserted at the access to the block A and
B. Regardless of the content of the FMR17 bit, access to other block and the internal RAM is
determined be PM17 bit setting.
Figure 17.5.1. FMR0 and FMR1 register
Rev. 2.00 Feb.15, 2007 ^{page 241} of 329
REJ09B0202-0200