M16C26A Datasheet, PDF (162/352 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
13. Serial I/O
(1) Example of Transmit Timing (Internal clock is selected)
Tc
Transfer clock
UiC1 register
TE bit
“1”
“0”
Write data to the UiTB register
UiC1 register
“1”
TI bit
“0”
“H”
CTSi
“L”
Transferred from UiTB register to UARTi transmit register
TCLK
Stopped pulsing because CTSi = “H”
CLKi
Stopped pulsing because the TE bit = “0”
TxDi
UiC0 register
“1”
TXEPT bit
“0”
SiTIC register
“1”
IR bit
“0”
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program
Tc = TCLK = 2(n + 1) / fj
fj: frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
n: value set to UiBRG register
i: 0 to 2
The above timing diagram applies to the case where the register bits are set as follows:
• The CKDIR bit in the UiMR register is set to "0" (internal clock)
• The CRD bit in the UiC0 register is set to "0" (CTS/RTS enabled); CRS bit is set to "0" (CTS selected)
• The CKPOL bit in the UiC0 register is set to "0" (transmit data output at the falling edge and receive data taken in at the rising edge of the
transfer clock)
• The UiIRS bit is set to "0" (an interrupt request occurs when the transmit buffer becomes empty): U0IRS bit is the bit 0 in the UCON register
U1IRS bit is the bit 1 in the UCON register, and U2IRS bit is the bit 4 in the U2C1 register.
(2) Example of Receive Timing (External clock is selected)
“1”
UiC1 register
RE bit
“0”
UiC1 register
TE bit
UiC1 register
TI bit
RTSi
CLKi
RxDi
UiC1 register
RI bit
“1”
“0”
Write dummy data to UiTB register
“1”
“0”
Transferred from UiTB register to UARTi transmit register
“H”
Even if the reception is completed, the RTS
“L”
does not change. The RTS becomes “L”
1 / fEXT
when the RI bit changes to “0” from “1”.
Receive data is taken in
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5
Transferred from UARTi receive register
“1”
to UiRB register
“0”
Read out from UiRB register
SiRIC register ^{“1”}
IR bit
“0”
Cleared to “0” when interrupt request is
accepted, or cleared to “0” by program
The above timing diagram applies to the case where the register bits are set
Make sure the following conditions are met when input
as follows:
to the CLKi pin before receiving data is high:
• The CKDIR bit in the UiMR register is set to "1" (external clock)
• UiC0 register TE bit is set to "1" (transmit enabled)
• The CRD bit in the UiC0 register is set to "0"(CTS/RTS enabled);
• UiC0 register RE bit is set to "1" (Receive enabled)
The CRS bit is set to "1" (RTS selected)
• Write dummy data to the UiTB register
• UiC0 register CKPOL bit is set to "0"(transmit data output at the falling edge and
receive data taken in at the rising edge of the transfer clock)
fEXT: frequency of external clock
Figure 13.1.1.1. Typical transmit/receive timings in clock synchronous serial I/O mode
Rev. 2.00 Feb.15, 2007 ^{page 145} of 329
REJ09B0202-0200