M16C26A Datasheet, PDF (332/352 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
19. Usage Notes
19.9 A/D Converter
1. Set ADCON0 (except bit 6), ADCON1 and ADCON2 registers when A/D conversion is stopped (before
a trigger occurs).
2. When the VCUT bit in the ADCON1 register is changed from “0” (Vref not connected) to “1” (VREF
connected), start A/D conversion after waiting 1 µs or longer.
3. To prevent noise-induced device malfunction or latchup, as well as to reduce conversion errors, insert
capacitors between the AVCC, VREF, and analog input pins (ANi(i=0 to 7), AN24, AN3i(i=0 to 2)) each
and the AVSS pin. Similarly, insert a capacitor between the VCC pin and the VSS pin. Figure 19.4 is an
example connection of each pin.
4. Make sure the port direction bits for those pins that are used as analog inputs are set to “0” (input
mode). Also, if the TGR bit in ADCON0 register is set to "1" (external trigger), make sure the port
___________
direction bit for the ADTRG pin is set to “0” (input mode).
5. When using key input interrupts, do not use any of the four AN4 to AN7 pins as analog inputs. (A key
input interrupt request is generated when the A/D input voltage goes low.)
6. The φAD frequency must be 10 MHz or less (12 MHz or less in M16C/26B). Without sample-and-hold
function, limit the φAD frequency to 250kHZ or more. With the sample and hold function, limit the φAD
frequency to 1MHZ or more.
7. When changing an A/D operation mode, select analog input pin again in the CH2 to CH0 bits in the
ADCON0 register and the SCAN1 to SCAN0 bits in the ADCON1 register.
VCC
C4
Microcomputer
VCC
VSS
AVCC
VREF
C1
AVSS
C3
ANi
VCC
C2
ANi: ANi(i=0 to 7), AN24, and AN3i (i=0 to 2)
NOTES:
1. C1 ≥ 0.47 µF, C2 ≥ 0.47 µF, C3 ≥ 100 pF, C4 ≥ 0.1 µF (reference)
2. Use thick and shortest possible wiring to connect capacitors.
Figure 19.3. Use of capacitors to reduce noise
Rev. 2.00 Feb.15, 2007 ^{page 315} of 329
REJ09B0202-0200