M16C26A Datasheet, PDF (175/352 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
13. Serial I/O
13.1.3 Special Mode 1 (I²C bus mode)(UART2)
I²C bus mode is provided for use as a simplified I²C bus interface compatible mode. Table 13.1.3.1 lists
the specifications of the I²C bus mode. Table 13.1.3.2 and 13.1.3.3 list the registers used in the I²C bus
mode and the register values set. Table 13.1.3.4 lists the I²C bus mode fuctions. Figure 13.1.3.1 shows
the block diagram for I²C bus mode. Figure 13.1.3.2 shows SCL2 timing.
As shown in Table 13.1.3.2, the microcomputer is placed in I²C bus mode by setting the SMD2 to SMD0
bits to ‘0102’ and the IICM bit to “1”. Because SDA2 transmit output has a delay circuit attached, SDA
output does not change state until SCL2 goes low and remains stably low.
Table 13.1.3.1. I²C bus Mode Specifications
Item
Specification
Transfer data format
• Transfer data length: 8 bits
Transfer clock
• During master
The CKDIR bit in the U2MR register is set to “0” (internal clock) : fj/ (2(n+1))
fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value in the U2BRG register 0016 to FF16
• During slave
Transmission start condition
Reception start condition
The CKDIR bit is set to “1” (external clock) : Input from SCL2 pin
• Before transmission can start, the following requirements must be met ⁽¹⁾
_ _{The TE bit in the U2C1 register is set to "1" (transmission enabled)}
_ _{The TI bit in the U2C1 register is set to "0" (data present in U2TB register)}
• Before reception can start, the following requirements must be met ⁽¹⁾
_ _{The RE bit in the U2C1 register is set to "1" (reception enabled)}
_ _{The TE bit in the U2C1 register is set to "1" (transmission enabled)}
_ _{The TI bit in the U2C1 register is set to "0" (data present in the UiTB register)}
Interrupt request
generation timing
Error detection
When start or stop condition is detected, acknowledge undetected, and acknowledge
detected
• Overrun error ⁽²⁾
This error occurs if the serial I/O started receiving the next data before reading the
U2RB register and received the 8th bit of the next data
Select function
• Arbitration lost
Timing at which the ABT bit in the U2RB register is updated can be selected
• SDA2 digital delay
No digital delay or a delay of 2 to 8 U2BRG count source clock cycles selectable
• Clock phase setting
With or without clock delay selectable
NOTES:
1. When an external clock is selected, the conditions must be met while the external clock is in the high state.
2. If an overrun error occurs, bits 8 to 0 in UiRB register are undefined. The IR bit in the SiRIC register remains
unchanged.
Rev. 2.00 Feb.15, 2007 ^{page 158} of 329
REJ09B0202-0200