M16C26A Datasheet, PDF (167/352 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
13. Serial I/O
13.1.2. Clock Asynchronous Serial I/O (UART) Mode
The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer
data format. Tables 13.1.2.1 lists the specifications of the UART mode.
Table 13.1.2.1. UART Mode Specifications
Item
Specification
Transfer data format
• Character bit (transfer data): Selectable from 7, 8 or 9 bits
• Start bit: 1 bit
• Parity bit: Selectable from odd, even, or none
• Stop bit: Selectable from 1 or 2 bits
Transfer clock
• The CKDIR bit in the UiMR(i=0 to 2) register is set to "0" (internal clock) : fj/(16(n+1))
fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of UiBRG register 0016 to FF16
• CKDIR bit is set to “1” (external clock ) : fEXT/(16(n+1))
fEXT: Input from CLKi pin. n :Setting value of UiBRG register 0016 to FF16
_______
_______
_______ _______
Transmission, reception control • Selectable from CTS function, RTS function or CTS/RTS function disable
Transmission start condition
• Before transmission can start, the following requirements must be met
_ _{The TE bit in the UiC1 register is set to "1" (transmission enabled)}
_ _{The TI bit in the UiC1 register "0" (data present in UiTB register)}
_______
_______
_ _{If CTS function is selected, input “L” to the CTSi pin}
Reception start condition
• Before reception can start, the following requirements must be met
_ _{The RE bit in the UiC1 register is set to "1" (reception enabled)}
_ _{Start bit detection}
Interrupt request
generation timing
• For transmission, one of the following conditions can be selected
_ _{The UiIRS bit} (2) _{is set to "0" (transmit buffer empty): when transferring data from the}
UiTB register to the UARTi transmit register (at start of transmission)
_ _{The UiIRS bit is set to "1" (transfer completed): when the serial I/O finished sending}
data from
the UARTi transmit register
• For reception
When transferring data from the UARTi receive register to the UiRB register (at
Error detection
completion of reception)
• Overrun error ⁽¹⁾
This error occurs if the serial I/O started receiving the next data before reading the
UiRB register and received the bit one before the last stop bit of the next data
• Framing error
This error occurs when the number of stop bits set is not detected
• Parity error
This error occurs when if parity is enabled, the number of 1’s in parity and
character bits does not match the number of 1’s set
• Error sum flag
This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered
Select function
• LSB first, MSB first selection
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7
can be selected
• Serial data logic switch (UART2)
This function reverses the logic of the transmit/receive data. The start and stop bits
are not reversed.
• TXD, RXD I/O polarity switch (UART2)
This function reverses the polarities of hte TXD pin output and RXD pin input. The
logic levels of all I/O data is reversed.
_______ _______
• Separate CTS/RTS pins (UART0)
_________
_________
CTS0 and RTS0 are input/output from separate pins
• UART1 pin remapping selection
The UART1 pin can be selected from the P67 to P64 or P73 to P70.
NOTES:
1. If an overrun error occurs, bits 8 to 0 in UiRB register are undefined. The IR bit in the SiRIC register remains
unchanged.
2. The U0IRS and U1IRS bits respectively are the bits "0" and "1" in the UCON register; the U2IRS bit is the bit 4 in
the U2C1 register.
Rev. 2.00 Feb.15, 2007 ^{page 150} of 329
REJ09B0202-0200