M16C26A Datasheet, PDF (158/352 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
13. Serial I/O
UART2 special mode register 3
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2SMR3
Address
037516
After reset
000X0X0X 2
Bit
symbol
Bit name
Function
RW
Nothing is assigned.
(b0) _{When write, set “0”. When read, its content is indeterminate.}
CKPH Clock phase set bit
0 : Without clock delay
1 : With clock delay
RW
Nothing is assigned.
(b2) _{When write, set “0”. When read, its content is indeterminate.}
NODC Clock output select bit 0 : CLKi is CMOS output
1 : CLKi is N-channel open drain output
RW
Nothing is assigned.
(b4) _{When write, set “0”. When read, its content is indeterminate.}
DL0 _{SDA digital delay}
setup bit ^{(1, 2)}
b7 b6 b5
0 0 0 : Without delay
RW
0 0 1 : 1 to 2 cycle(s) of UiBRG count source
DL1
0 1 0 : 2 to 3 cycles of UiBRG count source
0 1 1 : 3 to 4 cycles of UiBRG count source
RW
1 0 0 : 4 to 5 cycles of UiBRG count source
1 0 1 : 5 to 6 cycles of UiBRG count source
DL2
1 1 0 : 6 to 7 cycles of UiBRG count source
RW
1 1 1 : 7 to 8 cycles of UiBRG count source
NOTES:
1. The DL2 to DL0 bits are used to generate a delay in SDA2 output by digital means during I²C bus mode. In other than
I²C bus mode, set these bits to “0002” (no delay).
2. The amount of delay varies with the load on SCL2 and SDA2 pins. Also, when using an external clock, the amount of
delay increases by about 100 ns.
UART2 Special Mode Register 4
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2SMR4
Address
037416
After Reset
0016
Bit Symbol
Bit Name
Function
RW
STAREQ
Start condition
generate bit ⁽¹⁾
0: Clear
1: Start
RW
RSTAREQ
Restart condition
generate bit ⁽¹⁾
0: Clear
1: Start
RW
STPREQ ^{Stop condition}
0: Clear
1: Start
RW
STSPSEL SCL2, SDA2 output
0: Start and stop conditions not output
1: Start and stop conditions output
RW
ACKD ACK data bit
0: ACK
1: NACK
RW
ACKC ^{ACK data output}
0: Serial I/O data output
1: ACK data output
RW
SCLHI ^{SCL2 output stop}
0: Disabled
1: Enabled
RW
SWC9 SCL2 wait bit 3
0: SCL2 “L” hold disabled
1: SCL2 “L” hold enabled
RW
NOTE:
1. Set to “0” when each condition is generated.
Figure 13.1.9. U2SMR3 register and U2SMR4 register
Rev. 2.00 Feb.15, 2007 ^{page 141} of 329
REJ09B0202-0200