M16C26A Datasheet, PDF (111/352 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
12. Timer
12.1 Timer A
Figure 12.1.1 shows a block diagram of the timer A. Figures 12.1.2 to 12.1.4 show registers related to the
timer A.
The timer A supports the following four modes. Except in event counter mode, timers A0 to A4 all have the
same function. Use the TMOD1 to TMOD0 bits in the TAiMR register (i = 0 to 4) to select the desired mode.
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external device or overflows and underflows of
other timers.
• One-shot timer mode: The timer outputs a pulse only once before it reaches the minimum count
“000016.”
• Pulse width modulation (PWM) mode: The timer outputs pulses in a given width successively.
Clock source
selection
f1 or f2
f8
f32
fC32
• Timer
• One shot
• PWM
• Timer
(gate function)
Polarity
selection
TAiIN
(i = 0 to 4)
• Event counter
Clock selection
Data bus high-order bits
Data bus low-order bits
Low-order
8 bits
Reload register
High-order
8 bits
Clock selection
TABSR register
Counter
Up-count/down-count
Always counts down except
in event counter mode
(1)
TB2 overflow
(1)
TAj overflow
(j = i – 1. Note, however, that j = 4 when i = 0)
TAk overflow
(k = i + 1. Note, however, that k = 0 when i = 4)
To external
trigger circuit _{Down count}
UDF register
TAi
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
Addresses
038716 - 038616
038916 - 038816
038B16 - 038A16
038D16 - 038C16
038F16 - 038E16
TAj
Timer A4
Timer A0
Timer A1
Timer A2
Timer A3
TAk
Timer A1
Timer A2
Timer A3
Timer A4
Timer A0
TAiOUT
(i = 0 to 4)
Pulse output
Toggle flip-flop
NOTE:
1. Overflow or underflow
Figure 12.1.1. Timer A Block Diagram
Timer Ai mode register (i=0 to 4)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TA0MR to TA4MR
Address
After reset
039616 to 039A16
0016
Bit symbol
Bit name
Function
RW
TMOD0
b1 b0
Operation mode select bit _{0 0 : Timer mode}
RW
0 1 : Event counter mode
TMOD1
1 0 : One-shot timer mode
1 1 : Pulse width modulation
RW
(PWM) mode
MR0
Function varies with each
RW
MR1
operation mode
RW
MR2
RW
MR3
RW
TCK0
Count source select bit
Function varies with each
RW
TCK1
operation mode
RW
Figure 12.1.2. TA0MR to TA4MR Registers
Rev. 2.00 Feb.15, 2007 ^{page 94} of 329
REJ09B0202-0200