M16C26A Datasheet, PDF (194/352 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
13. Serial I/O
(1) Transmit Timing
Tc
Transfer Clock
TE bit in U2C1
"1"
register
"0"
TI bit in U2C1
"1"
register
"0"
TxD2
Parity Error Signal
returned from
Receiving End
RxD2 pin Level⁽¹⁾
TXEPT bit in U2 _"1"
C0 register
"0"
IR bit in S2TIC
"1"
register
"0"
Data is written to
the UARTi register
Start
bit
Parity Stop
bit bit
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
Data is transferred from the U2TB
register to the UART2 transmit
register
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
An "L" signal is applied from the SIM
card due to a parity error
ST D0 D1 D2 D3 D4 D5 D6 D7 P
SP
An interrupt routine
detects "H" or "L"
An interrupt routine detects
"H" or "L"
The above timing diagram applies to the case where data is
transferred in the direct format.
• U2MR register STPS bit = 0 (1 stop bit)
• U2MR register PRY bit = 1 (even)
• U2C0 register UFORM bit = 0 (LSB first)
• U2C1 register U2LCH bit = 0 (no reverse)
• U2C1 register U2IRSCH bit = 1 (transmit is completed)
Set to "0" by an interrupt request acknowledgement or by program
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of U2BRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
fEXT : frequency of U2BRG count source (external clock)
n : value set to U2BRG
(2) Receive Timing
TC
Transfer Clock
RE bit in U2C1
register
"1
"
"0
"
Transmit Waveform
from the
Transmitting End
TxD2
RxD2 pin Level⁽²⁾
Start
bit
Parity Stop
bit bit
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
TxD2 outputs "L" due
to a parity error
ST D0 D1 D2 D3 D4 D5 D6 D7 P
SP
RI bit in U2C1
"1"
register
"0
"
IR bit in S2RIC
"1"
register
"0"
Read the U2RB register
The above timing diagram applies to the case where data is
transferred in the direct format.
• U2MR register STPS bit = 0 (1 stop bit)
• U2MR register PRY bit = 1 (even)
• U2C0 register UFORM bit = 0 (LSB first)
• U2C1 register U2LCH bit = 0 (no reverse)
• U2C1 register U2IRSCH bit = 1 (transmit is completed)
Set to "0" by an interrupt request acknowledgement or by program
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of U2BRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
fEXT : frequency of U2BRG count source (external clock)
n : value set to U2BRG
NOTES:
1. Because TxD2 and RxD2 are connected, this is composite waveform consisting of the TxD2 output and the parity error
signal sent back from receiver.
2. Because TxD2 and RxD2 are connected, this is composite waveform consisting of the transmitter's transmit waveform
and the parity error signal received.
Figure 13.1.6.1. Transmit and Receive Timing in SIM Mode
Rev. 2.00 Feb.15, 2007 page 177 of 329
REJ09B0202-0200