M16C26A Datasheet, PDF (195/352 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
13. Serial I/O
Figure 13.1.6.2 shows the example of connecting the SIM interface. Connect TXD2 and RXD2 and apply
pull-up.
Microcomputer
TxD2
RxD2
SIM card
Figure 13.1.6.2. SIM Interface Connection
13.1.6.1 Parity Error Signal Output
The parity error signal is enabled by setting the U2ERE bit in the U2C1 register’ to “1”.
• When receiving
The parity error signal is output when a parity error is detected while receiving data. This is achieved
by pulling the TxD2 output low with the timing shown in Figure 13.1.6.1.1. If the R2RB register is read
while outputting a parity error signal, the PER bit is cleared to “0” and at the same time the TxD2 output
is returned high.
• When transmitting
A transmission-finished interrupt request is generated at the falling edge of the transfer clock pulse
that immediately follows the stop bit. Therefore, whether a parity signal has been returned can be
determined by reading the port that shares the RxD2 pin in a transmission-finished interrupt service
routine.
Transfer “H”
clock “L”
RxD2 “H”
“L”
ST D0 D1 D2 D3 D4 D5 D6 D7 P
TxD2 ^{“H”}
(1)
“L”
U2C1 register “1”
RI bit “0”
This timing diagram applies to the case where the direct format is implemented.
NOTE:
1. The output of microcomputer is in the high-impedance state
(pulled up externally).
SP
ST: Start bit
P: Even Parity
SP: Stop bit
Figure 13.1.6.1.1. Parity Error Signal Output Timing
Rev. 2.00 Feb.15, 2007 page 178 of 329
REJ09B0202-0200