M16C26A Datasheet, PDF (60/352 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
7. Clock Generation Circuit
Peripheral Clock Select Register ⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
00 000
Symbol
PCLKR
Address
025E16
After Reset
000000112
Bit Symbol
Bit Name
Function
RW
Timers A, B clock select bit
PCLK0
(Clock source for the timers A,
B, the timer S, the dead timer,
SI/O3, SI/O4 and multi-master
0: f2
1: f1
RW
I²C bus)
PCLK1
SI/O clock select bit
(Clock source for UART0 to
UART2)
0: f2SIO
1: f1SIO
RW
(b4-b2) ^{Reserved bit}
Set to 0
RW
PCLK5
Clock output function
expansion select bit
Refer to Table 7.5.3.1
RW
(b7-b6) ^{Reserved bit}
Set to 0
RW
NOTE:
1. Write to this register after setting the PRC0 bit in PRCR register to 1 (write enable).
Processeor Mode Register 2 ⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
PM2
Address
001E16
After Reset
XXX00000 2
Bit Symbol
Bit Name
Function
RW
PM20
Specifying wait when
accessing SFR(2)
0: 2 waits
1: 1 wait
RW
PM21
System clock protective
bit(3,4)
0: Clock is protected by PRCR
register
1: Clock modification disabled
RW
PM22
WDT count source
protective bit^(3,5)
0: CPU clock is used for the
watchdog timer count source
1: On-chip oscillator clock is used RW
for the watchdog timer count
source
(b3)
Reserved bit
Set to 0
RW
PM24
P85/NMI configuration bit(6,7)
0: P85 function (NMI disabled)
1: NMI function
RW
Nothing is assigned. When write, set to 0.
(b7-b5) _{When read, thecontent is undefined}
NOTES:
1. Write to this register after setting the PRC1 bit in the PRCR register to 1 (write enable).
2. The PM20 bit becomes effective when PLC07 bit in the PLC0 register is set to 1 (PLL on). Change the PM20
bit when the PLC07 bit is set to 0 (PLL off). Set the PM20 bit to 0 (2 waits) when PLL clock > 16MHz.
3. Once this bit is set to 1, it cannot be cleared to 0 by program.
4. Writting to the following bits has no effect when the PM21 bit is set to 1:
CM02 bit in the CM0 register
CM05 bit in the CM0 register (main clock is not halted)
CM07 bit in the CM0 register (CPU clock source does not change)
CM10 bit in the CM1 register (stop mode is not entered)
CM11 bit in the CM1 register (CPU clock source does not change)
CM20 bit in the CM2 register (oscillation stop, re-oscillation detection function settings do not change)
All bits in the PLC0 register (PLL frequency synthesizer setting do not change)
Do not execute WAIT instruction when the PM21 bit is set to 1.
5. Setting the PM22 bit to 1 results in the following conditions:
• The on-chip oscillator continues oscillating even if the CM21 bit in the CM2 register is set to "0" (main clock or
PLL clock) (system clock of count source selected by the CM21 bit is valid)
• The on-chip oscillator starts oscillating, and the on-chip oscillator clock becomes the watchdog timer
count source.
• The CM10 bit in the CM1 register cannnot be written. (Writing 1 has no effect, stop mode is not entered.)
• The watchdog timer does not stop in wait mode.
6. For NMI function, the PM24 bit must be set to 1(NMI function). Once this bit is set to 1, it cannot be set to 0 by
program.
7. SD input is valid regardless of the PM24 setting.
Figure 7.6. PCLKR Register and PM2 Register
Rev. 2.00 Feb.15, 2007 ^{page 43} of 329
REJ09B0202-0200