M16C26A Datasheet, PDF (170/352 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
13. Serial I/O
• Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
The transfer clock stops momentarily as CTSi is “H” when the stop bit is checked.
Tc
The transfer clock starts as the transfer starts immediately CTSi changes to “L”.
Transfer clock
UiC1 register
TE bit
“1”
“0”
UiC1 register
TI bit
“1”
“0”
“H”
CTSi
“L”
TxDi
UiC0 register
“1”
TXEPT bit
“0”
SiTIC register
“1”
IR bit
“0”
Write data to the UiTB register
Transferred from UiTB register to UARTi transmit register
Start
bit
Parity Stop
bit bit
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
Stopped pulsing
because the TE bit
= “0”
ST D0 D1
Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program
The above timing diagram applies to the case where the register bits are set
as follows:
• Set the PRYE bit in the UiMR register to "1" (parity enabled)
• Set the STPS bit in the UiMR register to "0" (1 stop bit)
• Set the CRD bit in the UiC0 register to "0" (CTS/RTS enabled),
the CRS bit to "0" (CTS selected)
• Set the UiIRS bit to "1" (an interrupt request occurs when transmit completed):
U0IRS bit is the UCON register bit 0, U1IRS bit is the UCON
register bit 1, and U2IRS bit is the U2C1 register bit 4
Tc = 16 (n + 1) / fj or 16 (n + 1) / fEXT
fj : frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
fEXT : frequency of UiBRG count source (external clock)
n : value set to UiBRG
i: 0 to 2
• Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)
Tc
Transfer clock
“1”
UiC1 register
TE bit
“0”
UiC1 register
“1”
TI bit
“0”
TxDi
UiC0 register
“1”
TXEPT bit
“0”
SiTIC register
“1”
IR bit
“0”
Write data to the UiTB register
Start
bit
Stop Stop
bit bit
Transferred from UiTB register to UARTi
transmit register
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SPSP
ST D0 D1
Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program
The above timing diagram applies to the case where the register bits are set
as follows:
• Set the PRYE bit in the UiMR register to "0" (parity disabled)
• Set the STPS bit in the UiMR register to "1" (2 stop bits)
• Set the CRD bit in the UiC0 register to "1"(CTS/RTS disabled)
• Set the UiIRS bit to "0" (an interrupt request occurs when transmit buffer
becomes empty):
U0IRS bit is the UCON register bit 0, U1IRS bit is the UCON
register bit 1, and U2IRS bit is the U2C1 register bit 4
Tc = 16 (n + 1) / fj or 16 (n + 1) / fEXT
fj : frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
fEXT : frequency of UiBRG count source (external clock)
n : value set to UiBRG
i: 0 to 2
Figure 13.1.2.1. Typical transmit timing in UART mode (UART0, UART1)
Rev. 2.00 Feb.15, 2007 ^{page 153} of 329
REJ09B0202-0200