M16C26A Datasheet, PDF (199/352 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
14. A/D Converter
A/D control register 0 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON0
Address
03D616
After reset
00000XXX 2
Bit symbol
Bit name
Function
RW
CH0
Analog Input Pin Select
Function varies with each operation mode
RW
Bit
CH1
RW
CH2
RW
MD0
MD1
TRG
ADST
CKS0
A/D Operation Mode
Select Bit 0
Trigger Select Bit
b4 b3
0 0 : One-shot mode or Delayed trigger mode 0,1 _RW
0 1 : Repeat mode
1 0 : Single sweep mode or
Simultaneous sample sweep mode
1 1 : Repeat sweep mode 0 or Repeat sweep
RW
mode 1
0 : Software trigger
RW
1 : Hardware trigger
A/D Conversion Start Flag 0 : A/D conversion disabled
1 : A/D conversion started
RW
Frequency Select Bit 0
See Table 14.2 A/D Conversion
Frequency Select
RW
NOTE:
1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.
A/D control register 1 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
After reset
0016
Bit symbol
Bit name
A/D Sweep Pin Select Bit
SCAN0
Function
RW
Function varies with each operation mode
RW
SCAN1
RW
A/D Operation Mode
0 : Other than repeat sweep mode 1
MD2
Select Bit 1
1 : Repeat sweep mode 1
RW
BITS
8/10-Bit Mode Select Bit 0 : 8-bit mode
1 : 10-bit mode
RW
CKS1 Frequency Select Bit 1
See Table 14.2 A/D Conversion
RW
Frequency Select
VCUT
VREF Connect Bit
(2)
0 : VREF not connected
1 : VREF connected
RW
(b7-b6)
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
NOTES:
1. If the ADCON1 register is rewritten during A/D conversion, the conversion result will be indeterminate.
2. If the VCUT bit is reset from “0” (VREF unconnected) to “1” (VREF connected), wait for 1 µs or more before starting
A/D conversion
A/D control register 2 ⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
ADCON2
Address
03D416
After reset
0016
Bit symbol
Bit name
SMP
A/D Conversion Method
Select Bit
Function
0 : Without sample and hold
1 : With sample and hold
ADGSEL0
ADGSEL1
A/D Input Group Select Bit
b2 b1
0 0 : Select port P10 group
0 1 : Select port P9 group (AN3i)
1 0 : Do not set
1 1 : Select port P9 group (AN24)
(b3)
Reserved Bit
Set to “0”
CKS2
Frequency Select Bit 2
See Table 14.2 A/D Conversion
Frequency Select
RW
RW
RW
RW
RW
RW
TRG1
Trigger Select Bit
Function varies with each operation
mode
RW
(b7-b6)
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
NOTE:
1. If the ADCON2 register is rewritten during A/D conversion, the conversion result will be indeterminate.
Figure 14.2 ADCON0 to ADCON2 Registers
Rev. 2.00 Feb.15, 2007 ^{page 182} of 329
REJ09B0202-0200