M16C26A Datasheet, PDF (138/352 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
12. Timer
Three-phase output buffer register(i=0,1) ⁽¹⁾
b7
b5 b4 b3 b2 b1 b0
Symbol
IDB0
IDB1
Address
034A16
034B16
Bit symbol
Bit name
DUi
U phase output buffer i
DUBi U phase output buffer i
DVi
V phase output buffer i
When reset
001111112
001111112
Function
RW
Write the output level
RW
0: Active level
1: Inactive level
RW
When read, these bits show the three-phase
output shift register value.
RW
DVBi V phase output buffer i
RW
DWi
W phase output buffer i
RW
DWBi W phase output buffer i
RW
(b7-b6)
Nothing is assigned. When write, set to "0". When read,
these contents are "0".
RO
NOTE:
1. The IDB0 and IDB1 register values are transferred to the three-phase shift register by a transfer trigger. The value
written to the IDB0 register aftera transfer trigger represents the output signal of each phase, and the next value written
to the IDB1 register at the falling edge of the timer A1, A2 or A4 one-shot pulse represents the output signal of each
phase.
Dead time timer ^{(1, 2)}
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DTT
Address
034C16
When reset
Indeterminate
Function
Setting range
RW
Assuming the set value = n, upon a start trigger the timer starts _{1 to 255}
counting the count souce selected by the INV12 bit and stops
after counting it n times. The positive or negative phase
whichever is going from an inactive to an active level changes
WO
at the same time the dead time timer stops.
NOTES:
1. Use MOV instruction to write to this register.
2. Effective when the INV15 bit is set to “0” (dead time timer enable). If the INV15 bit is set to “1”, the dead time timer is
disabled and has no effect.
Timer B2 Interrupt Occurrences Frequency Set Counter
b7 b6 b5 b4 b3
b0
Symbol
ICTB2
Address
034D16
After Reset
Indeterminate
Function
Setting Range
RW
If the INV01 bit is "0" (ICTB2 counter counted every
time timer B2 underflows), assuming the set value
1 to 15
= n, a timer B2 interrupt is generated at every níth
occurrence of a timer B2 underflow.
If the INV01 bit is "1" (ICTB2 counter count timing
WO
selected by the INV00 bit), assuming the set value
= n, a timer B2 interrupt is generated at every níth
occurrence of a timer B2 underflow that meets the
condition selected by the INV00 bit.
(1)
Nothing is assigned. When write, set to "0". When read, its content is
indeterminate.
NOTE:
1. Use MOV instruction to write to this register.
If the INV01 bit is set to "1", make sure the TB2S bit also is set to "0" (timer B2 count stopped) when writing to
this register. If the INV01 bit is set to "0", although this register can be written even when the TB2S bit is set to
"1" (timer B2 count start), do not write synchronously with a timer B2 underflow.
Figure 12.3.4. IDB0 Register, IDB1Register, DTT Register, and ICTB2 Register
Rev. 2.00 Feb.15, 2007 ^{page 121} of 329
REJ09B0202-0200