M16C26A Datasheet, PDF (54/352 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
6. Processor Mode
The internal bus consists of CPU bus, memory bus, and peripheral bus. Bus Interface Unit (BIU) is used to
interfere with CPU, ROM/RAM, and perpheral functions by controling CPU bus, memory bus, and periph-
eral bus. Figure 6.3 shows the block diagram of the internal bus.
CPU
CPU address bus
CPU data bus
DMAC
BIU
CPU clock
Clock
generation
circuit
Peripheral function
ROM
RAM
Memory address bus
Memory data bus
Timer
WDT
Serial I/O
ADC
.
.
.
.
I/O
Figure 6.3 Bus Block Diagram
The number of bus cycle varies by the internal bus. Table 6.1 lists the accessible area and bus cycle.
Table 6.1 Accessible Area and Bus Cycle
Accessible Area
Bus Cycle
SFR
PM20 bit = 0 (2 waits)
3 CPU clock cycles
PM20 bit = 1 (1 wait)
2 CPU clock cycles
ROM/RAM PM17 bit = 0 (no wait)
1 CPU clock cycle
PM17 bit = 1 (1 wait)
2 CPU clock cycles
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
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