M16C26A Datasheet, PDF (179/352 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
13. Serial I/O
Table 13.1.3.4. I²C bus Mode Functions
Function
Clock synchronous serial I/O I²C bus mode (SMD2 to SMD0 = 0102 , IICM = 1)
mode (SMD2 to SMD0 = 0012, _{IICM2 = 0}
IICM = 0)
(NACK/ACK interrupt)
IICM2 = 1
(UART transmit/ receive interrupt)
CKPH = 0
CKPH = 1 CKPH = 0
CKPH = 1
(No clock delay) (Clock delay) (No clock delay) (Clock delay)
Factor of interrupt number
10 ⁽¹⁾
(Refer to Fig.13.1.3.2.)
Start condition detection or stop condition detection
(Refer to Figure 13.1.3.2.1. STSPSEL Bit Function)
Factor of interrupt number
15 ⁽¹⁾
(Refer to Fig.13.1.3.2.)
Factor of interrupt number
16 ⁽¹⁾
1(Refer to Fig.13.1.3.2.)
UART2 transmission
Transmission started or
completed (selected by U2IRS)
UART2 reception
When 8th bit received
CKPOL = 0 (rising edge)
CKPOL = 1 (falling edge)
No acknowledgment
detection (NACK)
Rising edge of SCL2 9th bit
Acknowledgment detection
(ACK)
Rising edge of SCL2 9th bit
UART2 transmission UART2 transmission
Rising edge of
Falling edge of SCL2
SCL2 9th bit
next to the 9th bit
UART2 transmission
Falling edge of SCL2 9th bit
Timing for transferring data CKPOL = 0 (rising edge)
from the UART reception _{CKPOL = 1 (falling edge)}
shift register to the U2RB
register
Rising edge of SCL2 9th bit
Falling edge of
SCL2 9th bit
Falling and rising
edges of SCL2 9th
bit
UART2 transmission
output delay
Not delayed
Delayed
Functions of P70 pin
TxD2 output
SDA2 input/output
Functions of P71 pin
RxD2 input
SCL2 input/output
Functions of P72 pin
CLK2 input or output selected
(Cannot be used in I²C mode)
Noise filter width
15ns
200ns
Read RxD2 and SCL2 pin Possible when the
Always possible no matter how the corresponding port direction bit is set
levels
corresponding port direction bit
=0
Initial value of TxD2 and CKPOL = 0 (H)
SDA2 outputs
CKPOL = 1 (L)
The value set in the port register before setting I²C bus mode ⁽²⁾
Initial and end values of
SCL2
H
L
H
L
DMA1 factor (Refer to Fig. UART2 reception
14.1.3.2.)
Acknowledgment detection
(ACK)
UART2 reception
Falling edge of SCL2 9th bit
Store received data
1st to 8th bits are stored in
U2RB register bit 0 to bit 7
1st to 8th bits are stored in
U2RB register bit 7 to bit 0
1st to 7th bits are stored in U2RB register
bit 6 to bit 0, with 8th bit stored in U2RB
register bit 8
Read received data
U2RB register status is read
directly as is
1st to 8th bits are
stored in U2RB
register bit 7 to bit 0
(3)
Read U2RB register
Bit 6 to bit 0 as bit 7
to bit 1, and bit 8 as
bit 0 ⁽⁴⁾
NOTES:
1. If the source or cause of any interrupt is changed, the IR bit in the interrupt control register for the changed interrupt
may inadvertently be set to 1 (interrupt requested). (Refer to “Notes on interrupts” in Usage Notes) If one of the bits
shown below is changed, the interrupt source, the interrupt timing, etc. change. Therefore, always be sure to clear
the IR bit to 0 (interrupt not requested) after changing those bits. SMD2 to SMD0 bits in the U2MR register, IICM bit
in the U2SMR register, IICM2 bit in the U2SMR2 register, CKPH bit in the U2SMR3 register
2. Set the initial value of SDA2 output while the SMD2 to SMD0 bits in the U2MR register is set to ‘0002’ (serial I/O
disabled).
3. Second data transfer to U2RB register (Rising edge of SCL2 9th bit)
4. First data transfer to U2RB register (Falling edge of SCL2 9th bit)
Rev. 2.00 Feb.15, 2007 ^{page 162} of 329
REJ09B0202-0200