M16C26A Datasheet, PDF (36/352 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
3. Memory
3. Memory
Figure 3.1 is a memory map of the M16C/26A Group (M16C/26A, M16C/26B, M16C/26T). The M16C/26A
Group provides 1-Mbyte address space addresses 0000016 to FFFFF16.
The internal ROM is allocated lower address, beginning with address FFFFF16. For example, a 64-Kbyte
internal ROM area is allocated in addresses F000016 to FFFFF16. The flash memory version has two sets
of 2-Kbyte internal ROM area, block A and block B, for data space. These blocks are allocated addresses
F00016 to FFFF16.
The fixed interrupt vectors are allocated addresses FFFDC16 to FFFFF16 and they store the start address
of each interrupt routine.
The internal RAM is allocated higher addresses, beginning with address 0040016. For example, a 1-Kbyte
internal RAM area is allocated in addresses 0040016 to 007FF16. The internal RAM is used for temporarily
storing data. The area is also used as stacks when subroutines are called or interrupt requests are ac-
knowledged.
The SFR is allocated addresses 0000016 to 003FF16. The peripheral function control registers are allo-
cated here. All blank spaces within SFR location are reserved and cannot be accessed by users.
The special page vectors are allocated addresses FFE0016 to FFFDB16. They are used for the JMPS
instruction and JSRS instruction. Refer to the Renesas publication M16C/60 and M16C/20 Series Soft-
ware Manual for details.
0000016
0040016
Internal RAM
Size
Address XXXXX16
1K bytes
007FF16
2K bytes
00BFF16
Internal ROM
Size
Address YYYYY16
24K bytes
FA00016
48K bytes
64K bytes
F400016
F000016
XXXXX16
0F00016
0FFFF16
SFR
Internal RAM
Reserved
Internal ROM ⁽¹⁾
(Data space)
Reserved
YYYYY16
FFFFF16
Internal ROM⁽²⁾
(Program space)
NOTE:
1. Block A (2 Kbytes) and block B (2 Kbytes).
2. Do not write to the internal ROM in Mask ROM version.
Figure 3.1 Memory Map
FFE0016
Special page
vector table
FFFDC16
FFFFF16
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Watchdog timer
DBC
NMI
Reset
Rev. 2.00 Feb.15, 2007 ^{page 19} of 329
REJ09B0202-0200