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M16C26A Datasheet, PDF (266/352 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES | |||
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
17. Flash Memory Version
17.7.5 Block Erase
By writing âxx2016â in the first bus cycle and âxxD016â in the second bus cycle to the highest-order (even
addresse of a block) and the auto-programming/erasing (erase and erase verify) start. The FMR00 bit
in the FMR0 register indicates whether the auto-programming operation has been completed. The
FMR00 bit is set to â0â (busy) during the auto-erasing operation and â1â (ready) when the auto-erasing
operation is completed. When using the erase-suspend function in EW0 mode, the FMR46 bit in the
FMR4 register indicates whether a flash memory has entered erase-suspend mode. The FMR46 bit is
set to â0â during auto-erasing operation and â1â when the auto-erasing operation is completed (enter-
ing erase-suspend). After the completion of an auto-erasing operation, the FMR07 bit in the FMR0
register indicates whether or not the auto erasing-operation has been completed as expected. (Refer
to 17.8.4 Full Status Check). Also, each block disables erasing. (Refer to âTable 17.5.2.1â). Figure
17.7.5.1 shows a flow chart of the block erase command programming when not using the erase-
suspend function. Figure 17.7.5.2 shows a flow chart of the block erase command programming when
using an erase-suspend function. In EW1 mode, do not execute this command on the block where the
rewrite control program is allocated. In EW0 mode, the microcomputer enters read status register
mode as soon as the auto-erasing operation starts and the status register can be read. The SR7 bit in
the status register is set to â0â as soon as the auto-erasing operation starts. This bit is set to â1â when
the auto-erasing operation is completed. The microcomputer remains in read status register mode
until the read array command is written. Also excute the clear status register command and block
erase command at least 3 times until an erase error is not generated when an erase error is gener-
ated.
Start
Write command code âxx2016â(1)
Write âxxD016â to the highest-order
block address(1)
NO
FMR00=1?
YES
Full status check(2,3)
Block erase completed
NOTES:
1. Write the command code and data at even address.
2. Refer to "Figure 17.8.4.1. Full Status Check and Handling Porcedure for Each Error".
3. Execute the clear status register command and block erase command at least 3 times until an erase error is
not generated when an erase error is generated.
Figure 17.7.5.1. Flow Chart of Block Erase Command (when not using erase suspend function)
Rev. 2.00 Feb.15, 2007 page 249 of 329
REJ09B0202-0200
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