M16C26A Datasheet, PDF (91/352 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
9. Interrupt
9.4.4 Returning from an Interrupt Routine
The FLG register and PC in the state in which they were immediately before entering the interrupt se-
quence are restored from the stack by executing the REIT instruction at the end of the interrupt routine.
Thereafter the CPU returns to the program which was being executed before accepting the interrupt
request.
Return the other registers saved by a program within the interrupt routine using the POPM or similar
instruction before executing the REIT instruction.
9.5 Interrupt Priority
If two or more interrupt requests are generated while executing one instruction, the interrupt request that
has the highest priority is accepted.
For maskable interrupts (peripheral functions), any desired priority level can be selected using the ILVL2 to
ILVL0 bits. However, if two or more maskable interrupts have the same priority level, their interrupt priority
is resolved by hardware, with the highest priority interrupt accepted.
The watchdog timer and other special interrupts have their priority levels set in hardware. Figure 9.5.1
shows the priorities of hardware interrupts.
Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches
invariably to the interrupt routine.
Reset
NMI
High
DBC
Watchdog Timer,
Oscillation stop and re-oscillation
detection,
voltage down detection
Peripheral function
Single step
Address match
Low
Figure 9.5.1. Hardware Interrupt Priority
9.5.1 Interrupt Priority Resolution Circuit
The interrupt priority resolution circuit is used to select the interrupt with the highest priority among those
requested.
Figure 9.5.1.1 shows the circuit that judges the interrupt priority level.
Rev. 2.00 Feb.15, 2007 ^{page 74} of 329
REJ09B0202-0200