M16C26A Datasheet, PDF (231/352 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
15. CRC Calculation Circuit
CRC Data Register
(b15)
b7
(b8)
b0 b7
b0
Symbol
CRCD
Address
03BD16 to 03BC16
After Reset
Undefined
Function
CRC calculation result output
Setting Range RW
000016 to FFFF16 RW
CRC Input Register
b7
b0
Symbol
CRCIN
Data input
Address
03BE16
Function
After Reset
Undefined
Setting Range RW
0016 to FF16 RW
CRC Mode Register
b7
b0
Symbol
CRCMR
Address
03B616
After Reset
0XXXXXX02
BBit ist ySmymboblol
BiBt nitaNmaeme
Function
RW
CRCCRPCSPS ^{CRCCRCmomdoedpeoplyonlyonmoimalial}
sesleecleticotniobnitbit
0: X¹⁶+X¹²+X⁵+1 (CRC-CCITT)
1: X¹⁶+X¹⁵+X²+1 (CRC-16)
RW
NWor(itbthe6in-"bg01"i)swahsesnigNWwnorheittedhin.ingrgetoiasdtah, ^{sitshsiebgintc.eoTdnh.teInfvtnaiselucueensidsseainfridnye,} _{tsdeertmtoin0a.te if read.}
CCRRCCMMSS CRCCRmC omdoedseesleecleticotniobnitbit ^{0: LSB first}
RW
1: MSB first
SFR Snoop Address Register
(b15)
(b8)
b7
b0 b7
b0
Symbol
CRCSAR
Address
03B516 to 03B416
After Reset
00XXXXXX XXXXXXXX2
Bit Symbol
Bit Name
Function
RW
CRCSAR9-0 ^{CRC mode polynomial} SFR address to snoop
selection bit
RW
Nothing is assigned. If necessary, set to 0.
(b13-b10) _{When read, the content is undefined}
CRCSR
CRC snoop on read
enable bit
0: Disabled
1: Enabled⁽¹⁾
RW
CRCSW ^{CRC snoop on write}
0: Disabled
RW
enable bit
1: Enabled⁽¹⁾
NOTE:
1. Set bits CRCSR and CRCSW to 0 if the PLC07 bit in the PLC0 register is set to 1 (PLL on) and the PM20 bit in
the PM2 register is set to 0 (SFR access 2 wait).
Figure 15.2. CRCD, CRCIN, CRCMR, CRCSAR Register
Rev. 2.00 Feb.15, 2007 ^{page 214} of 329
REJ09B0202-0200