M16C26A Datasheet, PDF (153/352 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
13. Serial I/O
UARTi Transmit Buffer Register (i=0 to 2)⁽¹⁾
(b15)
(b8)
b7
b0 b7
b0
Symbol
U0TB
U1TB
U2TB
Address
03A316-03A216
03AB16-03AA16
037B16-037A16
After Reset
Indeterminate
Indeterminate
Indeterminate
Function
RW
Transmit data
WO
Nothing is assigned.
When write, set to "0". When read, its content is indeterminate.
NOTES:
1. Use MOV instruction to write to this register.
UARTi Receive Buffer Register (i=0 to 2)
(b15)
(b8)
b7
b0 b7
b0
Symbol
U0RB
U1RB
U2RB
Address
03A716-03A616
03AF16-03AE16
037F16-037E16
After Reset
Indeterminate
Indeterminate
Indeterminate
Bit
Symbol
Bit Name
Function
RW
(b7-b0)
Receive data (D7 to D0)
RO
(b8)
Receive data (D 8)
RO
Nothing is assigned.
(b10-b9) When write, set to "0". When read, its content is indeterminate.
ABT Arbitration lost detecting
flag ⁽²⁾
0 : Not detected
1 : Detected
RW
OER Overrun error flag ⁽¹⁾
0 : No overrun error
1 : Overrun error found
RO
FER Framing error flag ⁽¹⁾
0 : No framing error
1 : Framing error found
RO
PER Parity error flag ⁽¹⁾
0 : No parity error
1 : Parity error found
RO
SUM Error sum flag ⁽¹⁾
0 : No error
RO
1 : Error found
NOTES:
1. When the SMD2 to SMD0 bits in the UiMR register are set to “000 2” (serial I/O disabled) or the RE bit in the UiC1 register is set to “0” (reception
disabled), all of the SUM, PER, FER and OER bits are set to “0” (no error). The SUM bit is set to “0” (no error) when all of the PER, FER and OER
bits are set to “0” (no error). Also, the PER and FER bits are set to “0” by reading the lower byte of the UiRB register.
2. The ABT bit is set to “0” by setting to “0” by program. (Writing “1” has no effect.)
Nothing is assigned at the bit 11 in the U0RB and U1RB registers. When write, set to "0". When read, its content is "0".
UARTi Baud Rate Generation Register (i=0 to 2)^{(1, 2, 3)}
b7
b0
Symbol
U0BRG
U1BRG
U2BRG
Address
03A116
03A916
037916
After Reset
Indeterminate
Indeterminate
Indeterminate
Function
Assuming that set value = n, UiBRG divides the count source
by n + 1
NOTES:
1. Write to this register while serial I/O is neither transmitting nor receiving.
2. Use MOV instruction to write to this register.
The transfer clock is shown below when the setting value in the UiBRG register is set as n.
(1) When the CKDIR bit in the UiMR register to “0” (internal clock)
• Clock synchronous serial I/O mode
: fj/(2(n+1))
• Clock asynchronous serial I/O (UART) mode : fj/(16(n+1))
(2) When the CKDIR bit in the UiMR register to “1” (external clock)
• Clock synchronous serial I/O mode
: fEXT
• Clock asynchronous serial I/O (UART) mode : fEXT/(16(n+1))
fj : f1SIO, f2SIO, f8SIO, f32SIO
fEXT : Input from CLKi pin
3. Set the UiBRG register after setting the CLK1 and CLK0 bits in the UiC0 registers.
Setting Range
RW
0016 to FF16
WO
Figure 13.1.4. U0TB to U2TB registers, U0RB to U2RB registers, U0BRG to U2BRG registers
Rev. 2.00 Feb.15, 2007 ^{page 136} of 329
REJ09B0202-0200