M16C26A Datasheet, PDF (106/352 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
11. DMAC
11.2. DMA Transfer Cycles
Any combination of even or odd transfer read and write adresses is possible. Table 11.2.1 shows the
number of DMA transfer cycles. Table 11.2.2 shows the Coefficient j, k.
The number of DMAC transfer cycles can be calculated as follows:
No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k
Table 11.2.1 DMA Transfer Cycles
Transfer unit
8-bit transfers
(DMBIT= “1”)
16-bit transfers
(DMBIT= “0”)
Access address
Even
Odd
Even
Odd
No. of read cycles
1
1
1
2
No. of write cycles
1
1
1
2
Table 11.2.2 Coefficient j, k
Internal area
Internal ROM, RAM
No wait With wait
j1
2
SFR
1 wait
(1)
2 wait
(1)
2
3
k1
2
2
3
NOTE:
1. Depends on the set value of PM20 bit in PM2 register.
Rev. 2.00 Feb.15, 2007 page 89 of 329
REJ09B0202-0200