M16C26A Datasheet, PDF (222/352 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
14. A/D Converter
14.1.8 Delayed Trigger Mode 1
In delayed trigger mode 1, analog voltages applied to the selected pins are converted one-by-one to a
digital code. When the input of the ADTRG pin (falling edge) changes state from “H” to “L”, a single sweep
conversion is started. After completing the AN0 pin conversion, the AN1 pin is not sampled and converted
until the second ADTRG pin falling edge is generated. When the second ADTRG falling edge is generated,
The single sweep conversion of the pins after the AN1 pin is restarted. Table 14.1.8.1 shows the delayed
trigger mode 1 specifications. Figure 14.1.8.1 shows the operation example of delayed trigger mode 1.
Figure 14.1.8.2 to Figure 14.1.8.3 show each flag operation in the ADSTAT0 register that corresponds to
the operation example. Figure 14.1.8.4 shows the ADCON0 to ADCON2 registers in delayed trigger
mode 1. Figure 14.1.8.5 shows the ADTRGCON register in delayed trigger mode 1 and Table 15.1.8.2
shows the trigger select bit setting in delayed trigger mode 1.
Table 14.1.8.1 Delayed Trigger Mode 1 Specifications
Item
Function
A/D Conversion Start
Condition
A/D Conversion Stop
Condition
Specification
The SCAN1 to SCAN0 bits in the ADCON1 register and ADGSEL1 to ADGSEL0 bits
in the ADCON2 register select pins. Analog voltages applied to the selected pins are
converted one-by-one to a digital code. At this time, the ADTRG pin
falling edge starts AN0 pin conversion and the second ADTRG pin falling edge starts
conversion of the pins after AN1 pin
AN0 pin conversion start condition
The ADTRG pin input changes state from “H” to “L” (falling edge)⁽¹⁾
AN1 pin conversion start condition ⁽²⁾
The ADTRG pin input changes state from “H” to “L” (falling edge)
•When the second ADTRG pin falling edge is generated during or after A/D
conversion of the AN0 pin, input voltage of AN1 pin is sampled at the time of ADTRG
falling edge. The conversion of AN1 and the rest of the sweep starts when AN0
conversion is completed.
•When the ADTRG pin falling edge is generated again during single sweep conver
sion of pins after the AN1 pin, the conversion is not affected
•A/D conversion completed
•Set the ADST bit to "0" (A/D conversion halted)⁽³⁾
Interrupt Request
Single sweep conversion completed
Generation Timing
Analog Input Pin
Readout of A/D Conversion Result
Select from AN0 to AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins) and
AN0 to AN7 (8 pins)⁽⁴⁾
Readout one of the AN0 to AN7 registers that corresponds to the selected pins
NOTES:
___________
1. Do not generate the next ADTRG pin falling edge after the AN1 pin conversion is started until all selected pins
___________
complete A/D conversion. When an ADTRG pin falling edge is generated again during A/D conversion, its trigger
___________
is ignored. The falling edge of ADTRG pin, which was input after all selected pins complete A/D conversion, is
considered to be the next AN0 pin conversion start condition.
___________
___________
2. The ADTRG pin falling edge is detected synchronized with the operation clock φAD. Therefore, when the ADTRG pin
___________
falling edge is generated in shorter periods than φAD, the second ADTRG pin falling edge may not be detected. Do
___________
not generate the ADTRG pin falling edge in shorter periods than φAD.
3. Do not write “1” (A/D conversion started) to the ADST bit in delayed trigger mode 1. When write “1”, unexpected
interrupts may be generated.
4. AN30 to AN32 can be used in the same way as AN0 to AN7. However, all input pins need to belong to the same
group.
Rev. 2.00 Feb.15, 2007 ^{page 205} of 329
REJ09B0202-0200