M16C26A Datasheet, PDF (133/352 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
12. Timer
Timer Bi mode register (i= 0 to 1)
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol
TB0MR to TB1MR
Address
039B16 to 039C16
After reset
00XX00002
Bit symbol
Bit name
Function
RW
TMOD0
Operation Mode Select Bit
b1 b0
0 0 : Timer mode or A/D trigger mode
RW
TMOD1
RW
MR0
Invalid in A/D trigger mode
RW
MR1
Either "0" or "1" is enabled
RW
MR2
TB0MR register
Set to “0” in A/D trigger mode
RW
TB1MR register
Nothing is assigned. When write, set to “0”. When read, its
content is indeterminate
MR3
When write in A/D trigger mode, set to “0”. When read in A/D
trigger mode, its content is indeterminate.
RO
TCK0
Count Source Select Bit
(1)
b7 b6
0 0 : f1 or f2
RW
0 1 : f8
TCK1
1 0 : f32
RW
1 1 : fC32
NOTE:
1. When this bit is used in delayed trigger mode 0, set the same count source to the timer B0 and timer B1.
Figure 12.2.4.1 TBiMR Register in A/D Trigger Mode
Timer B2 special mode register (1)
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol
TB2SC
Address
039E16
After reset
X00000002
Bit symbol
Bit name
Function
RW
PWCOM Timer B2 Reload Timing 0 : Timer B2 underflow
Switch Bit (2)
1 : Timer A output at odd-numbered
RW
IVPCR1 ^{Three-Phase Output Port 0 : Three-phase output forcible cutoff}
SD Control Bit 1
by SD pin input (high impedance)
(3, 4, 7)
disabled
RW
1 : Three-phase output forcible cutoff
by SD pin input (high impedance)
enabled
TB0EN ^{Timer B0 Operation Mode 0 : Other than A/D trigger mode}
Select Bit
1 : A/D trigger mode (5)
RW
TB1EN ^{Timer B1 Operation Mode 0 : Other than A/D trigger mode}
Select Bit
1 : A/D trigger mode (5)
RW
TB2SEL Trigger Select Bit (6)
0 : TB2 interrupt
1 : Underflow of TB2 interrupt
RW
generation frequency setting counter [ICTB2]
(b6-b5) Reserved bits
Must set to "0"
RW
Nothing is assigned. When write, set to “0”.
(b7)
When read, its content is “0”.
NOTES:
1. Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enabled).
2. If the INV11 bit is "0" (three-phase mode 0) or the INV06 bit is "1" (triangular wave modulation mode), set this bit to
"0" (timer B2 underflow).
3. When setting the IVPCR1 bit to "1" (three-phase output forcible cutoff by SD pin input enabled), Set the PD8_5 bit to
"0" (= input mode).
4. Related pins are U(P80), U(P81), V(P72), V(P73), W(P74), W(P75). When a high-level ("H") signal is applied to the SD
pin and set the IVPCR1 bit to 0 after forcible cutoff, pins U, U, V, V, W, and W are exit from the high-impedance state.
If a low-level (“L”) signal is applied to the SD pin, three-phase motor control timer output will be disabled (INV03=0).
At this time, when the IVPCR1 bit is 0, pins U, U, V, V, W, and W become programmable I/O ports. When the IVPCR1
bit is set to 1, pins U, U, V, V, W, and W are placed in a high-impedance state regardless of which function of those
pins is used.
5. When this bit is used in delayed trigger mode 0, set the TB0EN and TB1EN bits to "1"(A/D trigger mode).
6. When setting the TB2SEL bit to "1" (underflow of TB2 interrupt generation frequency setting counter[ICTB2]), Set the
INV02 bit to "1" (three-phase motor control timer function).
7. Refer to 16.6 Digital Debounce function for SD input.
Figure 12.2.4.2 TB2SC Register
Rev. 2.00 Feb.15, 2007 ^{page 116} of 329
REJ09B0202-0200