M16C26A Datasheet, PDF (254/352 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
17. Flash Memory Version
17.4 CPU Rewrite Mode
In CPU rewrite mode, the user ROM area can be rewritten when the CPU executes software commands.
Therefore, the user ROM area can be rewritten directly while the microcomputer is mounted on-board
without using a ROM programmer, etc. Verify the Program and the Block Erase commands are executed
only on blocks in the user ROM area.
For interrupts requested during an erasing operation in CPU rewrite mode, the M16C/26A Group flash
module offers an erase-suspend function which the erasing operation to be suspended, and access made
available to the flash. Erase-write 0 (EW0) mode and erase-write 1 (EW1) mode are provided as CPU
rewrite mode. Table 17.4.1 shows the differences between erase-write 0 (EW0) and erase-write 1 (EW1)
modes. 1 wait is required for the CPU erase-write control.
Table 17.4.1. EW0 Mode and EW1 Mode
Item
EW0 mode
Operation mode
Single chip mode
Area where
User ROM area
rewrite control
program can be placed
Area where
The rewrite control program must be
rewrite control
transferred to any area other than
program can be
the flash memory (e.g., RAM) before
executed
being executed
Area which can be
User ROM area
rewritten
Software command
Restrictions
None
Mode after programming Read Status Register mode
or erasing
CPU state during auto- Operation
write and auto-erase
EW1 mode
Single chip mode
User ROM area
The rewrite control program can be
executed in the user ROM area
User ROM area
However, this excludes blocks
with the rewrite control program
• Program, block erase command
Cannot be executed in a block having
the rewrite control program
• Read status register command
Can not be used
Read Array mode
Hold state (I/O ports retain the state
before the command is executed
(1)
Flash memory status
detection ⁽²⁾
Condition for transferring
to erase-suspend ⁽³⁾
• Read the FMR00, FMR06 and
Read the FMR0 register's FMR00,
FMR07 bits in the FMR0 register by FMR06, and FMR07 bits in a program
a program
• Execute the read status register
command and read the SR7, SR5
and SR4 bits
Set the FMR40 and FMR41 bits in The FMR40 bit in the FMR4 register
the FMR4 register to "1" by program. is set to "1" and the interrupt request of
NOTES:
1. Do not generate a DMA transfer.
2. Block 1 and 0 are enabled to rewrite by setting the FMR02 bit in the FMR0 register to "1" and
setting the FMR16 bit in the FMR1 register to "1". Block 2 to 3 are enabled to rewrite by setting the
FMR16 bit in the FMR1 register to "1".
3. The time, until entering erase suspend and reading flash is enabled, is maximum td (SR-ES) after
satisfying the conditions.
Rev. 2.00 Feb.15, 2007 ^{page 237} of 329
REJ09B0202-0200