M16C26A Datasheet, PDF (191/352 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
13. Serial I/O
(1) The ABSCS bit in the U2SMR register (bus collision detect sampling clock select)
If ABSCS=0, bus collision is determined at the rising edge of the transfer clock
Transfer clock
TxD2
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP
RxD2
Input to TA0IN
Timer A0
If ABSCS is set to "1", bus collision is determined when timer
A0 (one-shot timer mode) underflows
.
(2) The ACSE bit in the U2SMR register (auto clear of transmit enable bit)
Transfer clock
TxD2
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP
RxD2
BCNIC register
IR bit ⁽¹⁾
U2C1 register
TE bit
If ACSE bit is set to "1"
automatically clear when bus collision
occurs), the TE bit is cleared to "0"
(transmission disabled) when
the IR bit in the BCNIC register is
set to "1" (unmatching detected).
(3) The SSS bit in the U2SMR register (Transmit start condition select)
If SSS bit is set to "0", the serial I/O starts sending data one transfer clock cycle after the transmission enable condition is met.
Transfer clock
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP
TxD2
Transmission enable condition is met
If SSS bit = 1, the serial I/O starts sending data at the rising edge ⁽¹⁾ of RxD2
CLK2
TxD2
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP
(2)
RxD2
NOTES:
1. The falling edge of RxD2 when the IOPOL is set to "0"; the rising edge of RxD2 when the IOPOL is set to "1".
2. The transmit condition must be met before the falling .edge (Note 1) of RxD.
This diagram applies to the case where the IOPOL is set to "1" (reversed)
Figure 13.1.5.1. Bus Collision Detect Function-Related Bits
Rev. 2.00 Feb.15, 2007 page 174 of 329
REJ09B0202-0200