M16C26A Datasheet, PDF (155/352 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
13. Serial I/O
UARTi Transmit/receive Control Rregister 0 (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
U0C0 to U2C0 03A416, 03AC16, 037C16
After Reset
000010002
Bit
Symbol
Bit Name
Function
RW
b1 b0
CLK0 BRG count source
select bit ⁽⁷⁾
0 0 : f1SIO or f2SIO is selected
0 1 : f8SIO is selected
RW
CLK1
1 0 : f32SIO is selected
1 1 : Do not set
RW
CRS CTS/RTS function
Effective when CRD is set to "0"
select bit ⁽³⁾
0 : CTS function is selected ⁽¹⁾
RW
1 : RTS function is selected
TXEPT Transmit register empty ^{0 : Data in transmit register (during transmission)}
flag
1 : No data in transmit register
RO
(transmission completed)
CRD CTS/RTS disable bit
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P60, P64 and P73 can be used as I/O ports)⁽⁶⁾
RW
NCH
Data output select bit⁽⁵⁾
0 : TxDi/SDA2 and SCL2 pins are CMOS output
1 : TxDi/SDA2 and SCL2 pins are N-channel open-drain output⁽⁴⁾
RW
CKPOL CLK polarity select bit ^{0 : Transmit data is output at falling edge of transfer clock}
and receive data is input at rising edge
1 : Transmit data is output at rising edge of transfer clock
RW
and receive data is input at falling edge
UFORM Transfer format select bit 0 : LSB first
RW
(2)
1 : MSB first
NOTES:
1. Set the corresponding port direction bit for each CTSi pin to “0” (input mode).
2. Effective when the SMD2 to SMD0 bits in the UMR register to "0012"(clock synchronous serial I/O mode) or "0102" (UART mode
transfer data 8 bits long). Set the UFORM bit to "1" when the SMD2 to SMD0 bits are set to "1012" (I²C bus mode) and "0" when
they are set to"1002" (UART mode transfer data 7 bits long) or "1102" ( UART mode transfer data 9 bits long).
3. CTS1/RTS1 can be used when the CLKMD1 bit in the UCON register is set to “0” (only CLK1 output) and the RCSP bit in the
UCON register is set to “0” (CTS0 /RTS0 not separated).
4. SDA2 and SCL2 are effective when i = 2.
5. When the SMD2 to SMD0 bits in UiMR regiser are set to “0002” (serial I/O disable), do not set NCH bit to “1” (TxDi/SDA2 and
SCL2 pins are N-channel open-drain output).
6. When the U1MAP bit in PACR register is “1” (P73 to P70), CTS/RTS pin in UART1 is assigned to P70.
7. When the CLK1 and CLK0 bit settings are changed, set the UiBRG register.
UART Transmit/receive Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UCON
Address
03B016
After Reset
X00000002
Bit Symbol
Bit Name
Function
RW
U0IRS
UART0 transmit interrupt 0: Transmit buffer empty (Tl = 1)
cause select bit
1: Transmission completed (TXEPT = 1)
RW
U1IRS
UART1 transmit interrupt 0: Transmit buffer empty (Tl = 1)
cause select bit
1: Transmission completed (TXEPT = 1)
RW
U0RRM
UART0 continuous
receive mode enable bit
0: Continuous receive mode disabled
1: Continuous receive mode enable
RW
U1RRM
UART1 continuous
receive mode enable bit
0: Continuous receive mode disabled
1: Continuous receive mode enabled
RW
CLKMD0
UART1 CLK/CLKS
select bit 0
CLKMD1
UART1 CLK/CLKS
select bit 1 (1)
RCSP
Separate UART0
CTS/RTS bit
Effective when CLKMD1 bit is set to “1”
0: Clock output from CLK1
RW
1: Clock output from CLKS1
0: Output from CLK1 only
1: Transfer clock output from multiple
RW
pins function selected
0: CTS/RTS shared pin
1: CTS/RTS separated (CTS0 supplied RW
from the P64 pin)(2)
Nothing is assigned. When write, set to “0”.
(b7)
When read, the content is indeterminate
NOTES:
1. To use more than one transfer clock output pins, set the CKDIR bit in the U1MR register to “0” (internal clock).
2. When the U1MAP bit in PACR register is set to “1” (P73 to P70), CTS0 is supplied from the P70 pin.
Figure 13.1.6. U0C0 to U2C0 registers and UCON register
Rev. 2.00 Feb.15, 2007 ^{page 138} of 329
REJ09B0202-0200