M16C26A Datasheet, PDF (281/352 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) ^{18. Electrical Characteristics (M16C/26A, M16C/26B)}
Table 18.4. Flash Memory Version Electrical Characteristic ⁽¹⁾:
Program Space and Data Space for U3 and U5, Program Space for U7 and U9
Symbol
Parameter
-
Program and Erase Endurance⁽³⁾
Standard
Min. Typ.⁽²⁾
100/1000^{(4, 11)}
-
Word Program Time (VCC=5.0V, Topr=25° C)
75
-
Block Erase Time
2-Kbyte Block
0.2
(VCC=5.0V, Topr=25° C)
8-Kbyte Block
0.4
16-Kbyte Block
0.7
32-Kbyte Block
1.2
td(SR-ES) Duration between Suspend Request and Erase Suspend
tPS
Wait Time to Stabilize Flash Memory Circuit
-
Data Hold Time ⁽⁵⁾
20
Max.
600
9
9
9
9
8
15
Unit
cycles
µs
s
s
s
s
ms
µs
years
Table 18.5. Flash Memory Version Electrical Characteristics ⁽⁶⁾: Data Space for U7 and U9 ⁽⁷⁾
Symbol
Parameter
-
Program and Erase Endurance^{(3, 8, 9)}
-
Word Program Time (VCC=5.0V, Topr=25° C)
Standard
Min. Typ.⁽²⁾
10000^{(4, 10)}
100
Max.
Unit
cycles
µs
-
Block Erase Time (VCC=5.0V, Topr=25° C)
(2-Kbyte block)
0.3
s
td(SR-ES) Duration between Suspend Request and Erase Suspend
tPS
Wait Time to Stabilize Flash Memory Circuit
-
Data Hold Time ⁽⁵⁾
20
8
ms
15
µs
years
NOTES:
1. Referenced to VCC = 2.7 to 5.5 V at Topr = 0 to 60° C (program space), -40 to 85° C (data space), unless
otherwise specified.
2. VCC = 5.0 V; Topr = 25° C
3. Program and erase endurance is defined as number of program-erase cycles per block.
If program and erase endurance is n cycle (n = 100, 1000, 10000), each block can be erased and programmed n
cycles.
For example, if a 2-Kbyte block A is erased after programming one-word data to each address 1,024 times,
this counts as one program and erase endurance. Data cannot be programmed to the same address more than
once without erasing the block. (rewrite prohibited).
4. Number of E/W cycles for which operation is guranteed (1 to minimum value are guaranteed).
5. Topr = 55° C
6. Referenced to VCC = 2.7 to 5.5 V at Topr = -40 to 85° C (U7) / -20 to 85° C ( U9) unless otherwise specified.
7. Table 18.5 applies for data space in U7 and U9 when program and erase endurance is more than 1,000 cycles.
Otherwise, use Table 18.4.
8. To reduce the number of program and erase endurance when working with systems requiring numerous rewrites,
write to unused word addresses within the block instead of rewrite. Erase block only after all possible addresses
are used. For example, an 8-word program can be written 128 times maximum before erase becomes necessary.
Maintaining an equal number of times erasure between block A and block B will also improve efficiency. It is
recommended to track the total number of erasure performed per block and to limit the number of erasure.
9. Execute the clear status register command and block erase command at least 3 times until an erase error is not
generated when an erase error is generated.
10. When executing more than 100 times rewrites, set one wait state per block access by setting the FMR17 bit in
the FMR1 register 1 to "1" (wait state). When accessing to all other blocks and internal RAM, wait state can be
set by the PM17 bit, regardless of the FMR17 bit setting value.
11. The program and erase endurance is 100 cycles for program space and data space in U3 and U5; 1,000
cycles for program space in U7 and U9.
12. Customers desiring E/W failure rate information should contact their Renesas technical support representative.
Erase suspend
request
(interrupt request)
FMR46
Rev. 2.00 Feb.15, 2007 ^{page 264} of 329
REJ09B0202-0200
td(SR-ES)