M16C26A Datasheet, PDF (47/352 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Voltage detection register 1
b7 b6 b5 b4 b3 b2 b1 b0
0000 000
Symbol
VCR1
Address
001916
After reset (2)
000010002
Bit symbol
Bit name
F unction
RW
(b2-b0)
Reserved bit
Must set to “0”
RW
VC13
Voltage down monitor flag
(1)
0:VCC < Vdet4
1:VCC ≥ Vdet4
RO
(b7-b4)
Reserved bit
Must set to “0”
RW
NOTES:
1. The VC13 bit is useful when the VC27 bit in the VCR2 register is set to "1" (voltage down detection circuit
enable). The VC13 bit is always "1" (VCC ≥ Vdet4) when the VC27 bit in the VCR2 register is set to "0"
(voltage down detection circuit disable).
2. This register does not change at software reset, watchdog timer reset and oscillation stop detection reset.
Voltage detection register 2 (1)
b7 b6 b5 b4 b3 b2 b1 b0
000000
Symbol
VCR2
Address
001A16
After reset (5)
0016
Bit symbol
(b5-b0)
VC26
Bit name
Reserved bit
Reset level monitor bit
(2, 3, 6)
VC27
Voltage down monitor
bit (4, 6)
Function
RW
Must set to “0”
RW
0: Disable reset level detection
circuit
1: Enable reset level detection ^RW
circuit
0: Disable voltage down
detection circuit
1: Enable voltage down
RW
detection circuit
NOTES:
1. Write to this register after setting the PRC3 bit in the PRCR register to “1” (write enable).
2. When not in stop mode, to use hardware reset 2, set the VC26 bit to “1” (reset level detection circuit enable).
3. VC26 bit is disabled in stop mode. (The microcomputer is not reset even if the voltage input to Vcc pin
becomes lower than Vdet3.)
4. When the VC13 bit in the VCR1 register and D42 bit in the D4INT register are used or the D40 bit is set to
“1” (voltage down detection interrupt enable), set the VC27 bit to “1” (voltage down detection circuit enable).
5. This register does not change at software reset, watchdog timer reset and oscillation stop detection reset.
6. The detection circuit does not start operation until td(E-A) elapses after the VC26 bit, or VC27 bit are set to
“1”.
Voltage down detection interrupt register (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
D4INT
Address
001F16
After reset
0016
Bit symbol
D40
D41
D42
D43
DF0
DF1
(b7-b6)
Bit name
interrupt enable bit (5)
STOP mode deactivation
control bit
(4)
Function
RW
0 : Disable
RW
1 : Enable
0: Disable (do not use the voltage
down detection
interrupt to get out of stop mode)
1: Enable (use the voltage down
RW
detection interrupt to get
out of stop mode)
Voltage change detection flag 0: Not detected
RW
(2)
1: Vdet4 passing detection
(3)
WDT overflow detect flag
0: Not detected
RW
1: Detected
(3)
Sampling clock select bit
b5b4
00 : CPU clock divided by 8
RW
01 : CPU clock divided by 16
10 : CPU clock divided by 32
11 : CPU clock divided by 64
RW
Nothing is assigned. When write, set to “0”. When read, its
content is “0”.
NOTES:
1. Write to this register after setting the PRC3 bit in the PRCR register to “1” (write enable).
2. Useful when the VC27 bit in the VCR2 register is set to “1” (voltage down detection circuit enabled). If the
VC27 bit is set to “0” (voltage down detection circuit disable), the D42 bit is set to “0” (Not detect).
3. This bit is set to “0” by writing a “0” in a program. (Writing a “1” has no effect.)
4. If the voltage down detection interrupt needs to be used to get out of stop mode again after once used for
that purpose, reset the D41 bit by writing a “0” and then a “1”.
5. The D40 bit is effective when the VC27 bit in the VCR2 register is set to “1”. To set the D40 bit to “1”, follow
the procedure described below.
(1) Set the VC27 bit to “1”.
(2) Wait for td(E-A) until the detection circuit is actuated.
(3) Wait for the sampling time (refer to “Table 5.5.1.2 Sampling Clock Periods”).
(4) Set the D40 bit to “1”.
Figure 5.5.2. VCR1 Register, VCR2 Register, and D4INT Register
Rev. 2.00 Feb.15, 2007 ^{page 30} of 329
REJ09B0202-0200
5. Reset