M16C26A Datasheet, PDF (171/352 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
13. Serial I/O
• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
UiBRG count
source
UiC1 register
RE bit
RxDi
Transfer clock
UiC1 register
RI bit
RTSi
SiRIC register
IR bit
“1”
“0”
Start bit
Stop bit
D0
D1 D7
Sampled “L”
Receive data taken in
Reception triggered when transfer clock
“1” is generated by falling edge of start bit
“0”
“H”
“L”
“1”
“0”
Transferred from UARTi receive
register to UiRB register
Read out from
UiRB register
Cleared to “0” when interrupt request is accepted, or cleared to “0” by program
The above timing diagram applies to the case where the register bits are set as follows:
• Set the PRYE bit in the UiMR register to "0"(parity disabled)
• Set the STPS bit in the UiMR register to "0" (1 stop bit)
• Set the CRD bit in the UiC0 register to "0" (CTSi/RTSi enabled), the CRS bit to "1" (RTSi selected)
i = 0 to 2
Figure 13.1.2.2. Receive Operation
13.1.2.1. Bit Rates
In UART mode, the frequency set by the UiBRG register (i=0 to 2) divided by 16 become the bit rates.
Table 13.1.2.1.1 lists example of bit rate and settings.
Table 13.1.2.1.1 Example of Bit Rates and Settings
Bit Rate
(bps)
1200
2400
4800
9600
14400
19200
28800
31250
38400
51200
Count Source
of BRG
f8
f8
f8
f1
f1
f1
f1
f1
f1
f1
Peripheral Function Clock : 16MHz Peripheral Function Clock : 20MHz
Set Value of BRG : n Actual Time (bps) Set Value of BRG : n Actual Time (bps)
103(67h)
1202
129(81h)
1202
51(33h)
2404
64(40h)
2404
25(19h)
4808
32(20h)
4735
103(67h)
9615
129(81h)
9615
68(44h)
14493
86(56h)
14368
51(33h)
19231
64(40h)
19231
34(22h)
28571
42(2Ah)
29070
31(1Fh)
31250
39(27h)
31250
25(19h)
38462
32(20h)
37879
19(13h)
50000
24(18h)
50000
Rev. 2.00 Feb.15, 2007 ^{page 154} of 329
REJ09B0202-0200