M16C26A Datasheet, PDF (82/352 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
9. Interrupt
9.2.2 Relocatable Vector Tables
The 256 bytes beginning with the start address set in the INTB register comprise a reloacatable vector
table area. Table 9.2.2.1 lists the relocatable vector tables. Setting an even address in the INTB register
results in the interrupt sequence being executed faster than in the case of odd addresses.
Table 9.2.2.1. Relocatable Vector Tables
Interrupt source
Vector address ⁽¹⁾
Address (L) to address (H)
Software interrupt
number
Reference
BRK instruction ⁽⁴⁾
(Reserved)
INT3
(Reserved)
+0 to +3 (0000 16 to 000316)
+16 to [phone] to 001316)
0
1 to 3
4
5 to 7
M16C/60, M16C/20
series software
manual
INT interrupt
INT5
(2)
INT4
(2)
+32 to [phone] to 002316)
8
+36 to [phone] to 002716)
9
INT interrupt
UART 2 bus collision detection (5)
+40 to [phone] to 002B16)
10
Serial I/O
DMA0
DMA1
+44 to +47 (002C 16 to 002F16)
11
DMAC
+48 to [phone] to 003316)
12
Key input interrupt
+52 to [phone] to 003716)
13
Key input interrupt
A/D
+56 to [phone] to 003B16)
14
A/D convertor
UART2 transmit, NACK2 (3)
+60 to +63 (003C 16 to 003F16)
15
UART2 receive, ACK2 (3)
+64 to [phone] to 004316)
16
UART0 transmit
UART0 receive
+68 to [phone] to 004716)
17
Serial I/O
+72 to [phone] to 004B16)
18
UART1 transmit
+76 to +79 (004C 16 to 004F16)
19
UART1 receive
+80 to [phone] to 005316)
20
Timer A0
+84 to [phone] to 005716)
21
Timer A1
+88 to [phone] to 005B16)
22
Timer A2
+92 to +95 (005C 16 to 005F16)
23
Timer A3
Timer A4
+96 to [phone] to 006316)
24
+100 to [phone] to 006716)
25
Timer
Timer B0
+104 to [phone] to 006B16)
26
Timer B1
+108 to +111 (006C 16 to 006F16)
27
Timer B2
+112 to [phone] to 007316)
28
INT0
INT1
+116 to [phone] to 007716)
29
+120 to [phone] to 007B16)
30
INT interrupt
INT2
+124 to +127 (007C 16 to 007F16)
31
Software interrupt (4)
+128 to [phone] to 008316)
32
to
to
+252 to +255 (00FC 16 to 00FF16)
63
M16C/60, M16C/20
series software
manual
NOTES:
1. Address relative to address in INTB.
2. Set the IFSR6 and IFSR7 bits in the IFSR register.
3. During I²C bus mode, NACK and ACK interrupts comprise the interrupt source.
4. These interrupts cannot be disabled using the I flag.
5. Bus collision detection:
During IEBus mode, this bus collision detection constitutes the cause of an interrupt.
During I²C bus mode, however, a start condition or a stop condition detection constitutes the cause of an interrupt.
Rev. 2.00 Feb.15, 2007 ^{page 65} of 329
REJ09B0202-0200