M16C26A Datasheet, PDF (152/352 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
13. Serial I/O
RxD2
No reverse
RxD data
reverse circuit
Reverse
IOPOL=0
IOPOL=1
1SP
STPS=0
SP
SP
2SP ^STPS=1
PAR
disabled
Clock
synchronous
type
PRYE=0 0
PAR
PAR ^PRYE=1
enabled
1
UART
SMD2 to SMD0
Clock
synchronous type
UART
(7 bits)
UART
(8 bits)
0
UART(7 bits)
0
1
UART
(9 bits)
1
Clock
synchronous type
UART
(8 bits)
UART
(9 bits)
UARTi receive register
0 0 0 0 0 0 0 D8
D7 D6 D5 D4 D3 D2 D1 D0
Logic reverse circuit + MSB/LSB conversion circuit
UART2 receive
buffer register
Address 037E16
Address 037F16
Data bus high-order bits
Data bus low-order bits
Logic reverse circuit + MSB/LSB conversion circuit
D8
D7 D6 D5 D4 D3 D2 D1 D0
UART2 transmit
buffer register
Address 037A16
Address 037B16
2SP ^STPS=1
SMD2 to SMD0
PAR
UART
enabled _{PRYE=1 1}
UART
(9 bits)
1
UART
(8 bits)
UART
(9 bits)
Clock
synchronous type
1
SP
SP
PAR
1SP
STPS=0
PRYE=0 0
PAR
disabled
0
Clock
synchronous
type
0
UART
(7 bits)
UART
(8 bits)
0 UART(7 bits)
UARTi transmit register
Clock
synchronous type
Error signal output
U2ERE disable
=0
U2ERE
=1
Error signal
output circuit
Error signal output
enable
IOPOL ^{No reverse}
=0
TxD data
reverse circuit
IOPOL
=1
Reverse
SP: Stop bit
PAR: Parity bit
TxD2
SMD2 to SMD0, STPS, PRYE, IOPOL, CKDIR : Bit in the U2MR register
U2ERE : Bit in the U2C1 register
Figure 13.1.3. Block diagram of UART2 transmit/receive unit
Rev. 2.00 Feb.15, 2007 ^{page 135} of 329
REJ09B0202-0200