M16C26A Datasheet, PDF (192/352 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
13. Serial I/O
13.1.6 Special Mode 4 (SIM Mode) (UART2)
Based on UART mode, this is an SIM interface compatible mode. Direct and inverse formats can be
implemented, and this mode allows output of a low from the TxD2 pin when a parity error is detected.
Tables 13.1.6.1 lists the specifications of SIM mode. Table 13.1.6.2 lists the registers used in the SIM
mode and the register values set.
Table 13.1.6.1. SIM Mode Specifications
Item
Transfer data format
Transfer clock
Transmission start condition
Reception start condition
Interrupt request
generation timing
(2)
Error detection
Specification
• Direct format
• Inverse format
• The CKDIR bit in the U2MR register is set to “0” (internal clock) : fi/(16(n+1))
fi = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value in U2BRG register 0016 to FF16
• The CKDIR bit is set to “1” (external clock ) : fEXT/(16(n+1))
fEXT: Input from CLK2 pin. n: Setting value in U2BRG register 0016 to FF16
• Before transmission can start, the following requirements must be met
_ _{The TE bit in the U2C1 register is set to "1" (transmission enabled)}
_ _{The TI bit in the U2C1 register is set to "0" (data present in U2TB register)}
• Before reception can start, the following requirements must be met
_ _{The RE bit in the U2C1 register is set to "1" (reception enabled)}
_ _{Start bit detection}
• For transmission
When the serial I/O finished sending data from the U2TB transfer register (the U2IRS bit
is set to "1")
• For reception
When transferring data from the UART2 receive register to the U2RB register (at
completion of reception)
• Overrun error ⁽¹⁾
This error occurs if the serial I/O started receiving the next data before reading the
U2RB register and received the bit one before the last stop bit of the next data
• Framing error
This error occurs when the number of stop bits set is not detected
• Parity error
During reception, if a parity error is detected, parity error signal is output from the
TxD2 pin.
During transmission, a parity error is detected by the level of input to the RXD2 pin
when a transmission interrupt occurs
• Error sum flag
This flag is set to "1" when any of the overrun, framing, and parity errors is encountered
NOTES:
1. If an overrun error occurs, bits 8 to 0 in UiRB register are undefined. The IR bit in the SiRIC register remains
unchanged.
2. A transmit interrupt request is generated by setting the U2IRS bit in the U2C1 register to “1” (transmission com-
plete) and the U2ERE bit to “1” (error signal output) after reset. Therefore, when using SIM mode, be sure to clear
the IR bit to “0” (no interrupt request) after setting these bits.
Rev. 2.00 Feb.15, 2007 page 175 of 329
REJ09B0202-0200