M16C26A Datasheet, PDF (89/352 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
9. Interrupt
9.4.3 Saving Registers
In the interrupt sequence, the FLG register and PC are saved to the stack.
At this time, the 4 high-order bits of the PC and the 4 high-order (IPL) and 8 low-order bits in the FLG
register, 16 bits in total, are saved to the stack first. Next, the 16 low-order bits of the PC are saved. Figure
9.4.3.1 shows the stack status before and after an interrupt request is accepted.
The other necessary registers must be saved in a program at the beginning of the interrupt routine. Use
the PUSHM instruction, and all registers except SP can be saved with a single instruction.
Address
MSB
Stack
LSB
m–4
m–3
m–2
m–1
m
Content of previous stack
m + 1 ^{Content of previous stack}
[SP]
SP value before
interrupt request is
accepted.
Address
Stack
MSB
LSB
m–4
m–3
m–2
PCL
PCM
FLGL
m–1
FLGH
PCH
m
Content of previous stack
m + 1 Content of previous stack
[SP]
New SP value
Stack status before interrupt request
is acknowledged
Stack status after interrupt request
is acknowledged
Figure 9.4.3.1. Stack Status Before and After Acceptance of Interrupt Request
Rev. 2.00 Feb.15, 2007 ^{page 72} of 329
REJ09B0202-0200