M16C26A Datasheet, PDF (183/352 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
13. Serial I/O
13.1.3.4 Transfer Clock
Data is transmitted/received using a transfer clock like the one shown in Figure 13.1.3.2.1.
The CSC bit in the U2SMR2 register is used to synchronize the internally generated clock (internal
SCL2) and an external clock supplied to the SCL2 pin. In cases when the CSC bit is set to “1” (clock
synchronization enabled), if a falling edge on the SCL2 pin is detected while the internal SCL2 is high,
the internal SCL2 goes low, at which time the U2BRG register value is reloaded with and starts count-
ing in the low-level interval. If the internal SCL2 changes state from low to high while the SCL2 pin is
low, counting stops, and when the SCL2 pin goes high, counting restarts.
In this way, the UART2 transfer clock is comprised of the logical product of the internal SCL2 and SCL2
pin signal. The transfer clock works from a half period before the falling edge of the internal SCL2 1st
bit to the rising edge of the 9^th bit. To use this function, select an internal clock for the transfer clock.
The SWC bit in the U2SMR2 register allows to select whether the SCL2 pin should be fixed to or freed
from low-level output at the falling edge of the 9th clock pulse.
If the SCLHI bit in the U2SMR4 register is set to “1” (enabled), SCL2 output is turned off (placed in the
high-impedance state) when a stop condition is detected.
Setting the SWC2 bit in the U2SMR2 register is set to "1" (0 output) makes it possible to forcibly output
a low-level signal from the SCL2 pin even while sending or receiving data. Clearing the SWC2 bit to “0”
(transfer clock) allows the transfer clock to be output from or supplied to the SCL2 pin, instead of
outputting a low-level signal.
If the SWC9 bit in the U2SMR4 register is set to “1” (SCL hold low enabled) when the CKPH bit in the
U2SMR3 register is set to "1", the SCL2 pin is fixed to low-level output at the falling edge of the clock
pulse next to the ninth. Setting the SWC9 bit is set to "0" (SCL hold low disabled) frees the SCL2 pin
from low-level output.
13.1.3.5 SDA Output
The data written to the bit 7 to bit 0 (D7 to D0) in the U2TB register is sequentially output beginning with
D7. The ninth bit (D8) is ACK or NACK.
The initial value of SDA2 transmit output can only be set when IICM is set to "1" (I²C Bus mode) and
the SMD2 to SMD0 bits in the the U2MR register are set to ‘0002’ (serial I/O disabled).
The DL2 to DL0 bits in the U2SMR3 register allow to add no delays or a delay of 2 to 8 U2BRG count
source clock cycles to SDA2 output.
Setting the SDHI bit in the U2SMR2 register is set to "1" (SDA output disabled) forcibly places the
SDA2 pin in the high-impedance state. Do not write to the SDHI bit synchronously with the rising edge
of the UART2 transfer clock. This is because the ABT bit may inadvertently be set to “1” (detected).
13.1.3.6 SDA Input
When the IICM2 bit is set to "0", the 1st to 8th bits (D7 to D0) of received data are stored in the bit 7 to
bit 0 in the U2RB register. The 9th bit (D8) is ACK or NACK.
When the IICM2 bit is set to "1", the 1st to 7th bits (D7 to D1) of received data are stored in the bit 6 to
bit 0 in the U2RB register and the 8th bit (D0) is stored in the bit 8 in the U2RB register. Even when the
IICM2 bit is set to "1", providing the CKPH bit to "1", the same data as when the IICM2 bit is set to "0"
can be read out by reading the U2RB register after the rising edge of the corresponding clock pulse of
9th bit.
Rev. 2.00 Feb.15, 2007 ^{page 166} of 329
REJ09B0202-0200