M16C26A Datasheet, PDF (49/352 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
5. Reset
5.5.1 Voltage Down Detection Interrupt
If the D40 bit in the D4INT register is set to “1” (voltage down detection interrupt enabled), the voltage
down detection interrupt request is generated when the voltage applied to the VCC pin crosses the
Vdet4 voltage level. The voltage down detection interrupt shares the same interrupt vector with the
watchdog timer interrupt and oscillation stop, re-oscillation detection interrupt.
Set the D41 bit in the D4INT register to “1” (enabled) to use the voltage down detection interrupt to exit
stop mode.
The D42 bit in the D4INT register is set to “1” as soon as the voltage applied to the VCC pin reaches
Vdet4 due to the voltage rise and voltage drop. When the D42 bit changes “0” to “1”, the voltage down
detection interrupt request is generated. Set the D42 bit to “0” by program. However, when the D41
bit is set to “1” and the microcomputer is in stop mode, the voltage down detection interrupt request is
generated regardless of the D42 bit state if the voltage applied to the VCC pin is detected to be above
Vdet4. The microcomputer then exits stop mode.
Table 5.5.1.1 shows how the voltage down detection interrupt request is generated.
The DF1 to DF0 bits in the D4INT register determine the sampling period that detects the voltage
applied to the VCC pin reaches Vdet4. Table 5.5.1.2 shows the sampling periods.
Table 5.5.1.1 Voltage Down Detection Interrupt Request Generation Conditions
Operation Mode
Normal
Operation
Mode⁽¹⁾
VC27 Bit
Wait Mode⁽²⁾
1
D40 Bit
1
D41 Bit
D42 Bit
0 to 1
0 to 1
CM02 Bit
0
1
VC13 Bit
0 to 1⁽³⁾
1 to 0⁽³⁾
0 to 1⁽³⁾
1 to 0⁽³⁾
0 to 1
Stop Mode⁽²⁾
1
0
0 to 1
– : “0”or “1”
NOTES:
1. The status except the wait mode and stop mode is handled as the normal mode.(Refer to 7. Clock generating circuit)
2. Refer to 5.5.2 Limitations on stop mode, 5.5.3 Limitations on wait mode.
3. An interrupt request for voltage reduction is generated a sampling time after the value of the VC13 bit has changed.
See the Figure 5.5.1.2 Voltage Down Detection Interrupt Generation Circuit Operation Example for details.
Table 5.5.1.2 Sampling Periods
CPU
Clock
(MHz)
Sampling Period (µs)
DF1 to DF0=00
DF1 to DF0=01
DF1 to DF0=10
DF1 to DF0=11
(CPU clock divided by 8) (CPU clock divided by 16) (CPU clock divided by 32) (CPU clock divided by 64)
16
3.0
6.0
12.0
24.0
Rev. 2.00 Feb.15, 2007 ^{page 32} of 329
REJ09B0202-0200