M16C26A Datasheet, PDF (172/352 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
13. Serial I/O
13.1.2.2. Counter Measure for Communication Error
If a communication error occurs while transmitting or receiving in UART mode, follow the procedure
below.
• Resetting the UiRB register (i=0 to 2)
(1) Set the RE bit in the UiC1 register to “0” (reception disabled)
(2) Set the RE bit in the UiC1 register to “1” (reception enabled)
• Resetting the UiTB register (i=0 to 2)
(1) Set the SMD2 to SMD0 bits in UiMR register “0002” (Serial I/O disabled)
(2) Set the SMD2 to SMD0 bits in UiMR register “0012”, “1012”, “1102”
(3) “1” is written to RE bit in the UiC1 register (reception enabled), regardless of the TE bit in the UiC1
register
13.1.2.3. LSB First/MSB First Select Function
As shown in Figure 14.1.2.3.1, use the UFORM bit in the UiC0 register to select the transfer format.
This function is valid when transfer data is 8 bits long.
(1) When the UFORM bit in the UiC0 register is set to "0" (LSB first)
CLKi
TXDi
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
RXDi
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
(2) When the UFORM bit in the UiC0 register "1" (MSB first)
CLKi
TXDi
ST D7 D6 D5 D4 D3 D2 D1 D0 P SP
RXDi
ST D7 D6 D5 D4 D3 D2 D1 D0 P SP
NOTE:
1. This applies to the case where the CKPOL bit in the UiC0 register is set to "0"
(transmit data output at the falling edge and the receive data taken in at the rising
edge of the transfer clock), the UiLCH bit in the UiC1 register is set to "0" (no
reverse), the STPS bit in the UiMR register is set to "0" (1 stop bit) and the PRYE
bit in the UiMR register is set to "1" (parity enabled).
i = 0 to 2
Figure 13.1.2.3.1. Transfer Format
ST: Start bit
P: Parity bit
SP: Stop bit
Rev. 2.00 Feb.15, 2007 ^{page 155} of 329
REJ09B0202-0200